US 6,616,394 B1Granted

Apparatus for processing wafers

AssigneeSilicon Valley Group, Inc.

InventorJae Heon Park

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Abstract

Systems and methods are described for wafer processing. A wafer processing apparatus includes: a first wafer transporter; a process station coupled to the first wafer transporter, the process station including: a first plurality of wafer processing stacks, each of the plurality of wafer processing stacks including a plurality of wafer processing modules, and a second wafer transporter coupled to the plurality of wafer processing modules, each of the plurality of wafer processing modules adjacent, and accessible by, the second wafer transporter; and a third wafer transporter coupled to the process station, wherein any of the plurality of wafer processing modules in any of the plurality of wafer processing stacks can be accessed by at least two adjacent wafer transporters from among the first, second and third wafer transporter. The systems and methods provide advantages from minimizing pre-process and/or post-process times, minimizing variation of the pre-process and/or post-process times and reducing robot over utilization.

Claims8

Dependent claims

A semiconductor wafer processing apparatus comprising:

a first wafer process station including:
a first main wafer transporter for handling semiconductor wafers within the first wafer process station, and a first plurality of wafer processing stacks containing process modules that are positioned in a polygonal configuration substantially around the first main wafer transporter;
a second wafer process station disposed adjacent to the first wafer process station, and including:
a second main wafer transporter for handling semiconductor wafers within the second wafer process station;
and a second plurality of wafer processing stacks containing process modules that are positioned in a polygonal configuration substantially around the second main wafer transporter,
a cassette end section for storing semiconductor wafers, and having a cassette wafer transporter that bidirectionally transports semiconductor wafers beyond the polygonal configuration of each respective wafer process station, and between at least one wafer processing stack in each wafer process station and the cassette end section;
and
a stepper interface section having a stepper wafer transporter that bidirectionally transports semiconductor wafers beyond the polygonal configuration of each respective wafer process station, and between at least one wafer processing stack in each wafer process station and the stepper interface section, wherein at least some of the process modules in each wafer process station are directly accessible by the cassette wafer transporter and the stepper wafer transporter.

5 more elements

Dependencies are inferred from the claim text.