Back to results
US 6,611,023 B1Granted
Field effect transistor with self alligned double gate and method of forming same
AssigneeAdvanced Micro Devices, Inc.
InventorsWilliam G. En, Srinath Krishnan
Life of this patent
Estimating the term…
Abstract
A fully depleted silicon on insulator (SOI) field effect transistor (FET) includes a gate positioned above a channel region and an aligned back gate positioned below the channel region and the buried oxide later. Alignment of the back gate with the gate is achieved utilizing a disposable gate process and retrograde doping of the backgate.
Claims9
A field effect transistor formed in a semiconductor substrate comprising:
- a) an active region, including a central channel region and a source region and a drain region on opposing sides of the central channel region;
- b) an upper gate positioned above the central channel region and isolated from the central channel region by an insulating gate oxide layer;
- c) a back gate positioned below the central channel region and isolated from the central channel region by an insulating oxide layer;
- and
- d) an isolation trench region positioned about the periphery of the active region and including a conductive via positioned therein for electrically coupling the upper gate to the back gate.
2 more elements
A semiconductor device including a plurality of field effect transistors formed on a semiconductor substrate, the device comprising:
- a) an insulating oxide layer positioned within the semiconductor substrate and separating a device layer portion of the semiconductor substrate form a bulk portion of the semiconductor substrate;
- b) an insulating trench pattern positioned within the device layer and isolating each of the plurality of field effect transistors and each of the plurality of field effect transistors comprises:
- i) an active region positioned within the device layer and including a central channel region and a source region and a drain region on opposing sides of the central channel region;
- ii) an upper gate positioned above the central channel region and isolated from the central channel region by an insulating gate oxide layer;
- iii) a back gate positioned below the central channel region and within the bulk portion of the semiconductor substrate and isolated from the central channel region by insulating oxide layer;
- and
- iv) a conductive via positioned within the insulating trench pattern for electrically coupling the upper gate to the back gate.
4 more elements
Dependencies are inferred from the claim text.