US 6,611,015 B2 · Semiconductor device including dummy upper electrode

Abstract

A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.

Claims29

Dependent claims

A semiconductor device comprising:

a semiconductor substrate;
a memory cell block including a plurality of transistors formed in series on the semiconductor substrate, the memory transistors having first and second impurity-diffused regions and gates formed respectively between the first and second impurity-diffused regions and being connected in series, a plurality of memory cells each having a lower electrode connected to the first impurity-diffused region, a ferroelectric film formed on the lower electrode, and a first upper electrode formed on the ferroelectric film and being connected to the second impurity-diffused region;
a block selecting transistor formed on the semiconductor substrate and being connected to one end of the memory cell block;
and
a second upper electrode formed adjoining the block selecting transistor and being disconnected from the first upper electrode of the memory cell.

2 more elements

A semiconductor memory device comprising:

a semiconductor substrate;
a plurality of memory transistor units formed on the semiconductor substrate and including a plurality of memory transistors having first and second impurity-diffused regions and a gate formed between the first and second impurity-diffused regions and being connected in series;
a plurality of plug electrodes respectively connected individually to a corresponding first impurity-diffused region;
a block selecting transistor formed on the semiconductor substrate and adjoined to one memory transistor in one end of the memory transistor units, and having impurity-diffused regions and a gate;
a first wiring connected to the second impurity-diffused region in said one end of the memory transistor units;
a lower electrode connected to the plug electrode connected to the first impurity-diffused region of the memory transistor in said one end of the memory cell block;
a ferroelectric film formed on the lower electrode;
a first upper electrode formed on the ferroelectric film and being connected to the first wiring;
a second upper electrode formed on the ferroelectric film and being disconnected from the memory transistor, the plug electrode, the block selecting transistor and the first wiring;
and
an insulating film formed over the semiconductor substrate, the memory transistors, the plug electrode, the first and second upper electrodes, the ferroelectric film, and the lower electrode.

8 more elements

A semiconductor memory device comprising:

a semiconductor substrate;
a first memory transistor formed on the semiconductor substrate, and having first and second impurity-diffused regions and a first gate;
a first plug electrode connected to the first impurity-diffused region;
a block selecting transistor formed on the semiconductor substrate and being adjoined to the memory transistor, and having impurity-diffused regions and a second gate;
a first wiring connected to the second impurity-diffused regions of the first memory transistor;
a first lower electrode connected to the first plug electrode;
a first ferroelectric film formed on the lower electrode;
a first upper electrode formed on the first ferroelectric film and being connected to the first wiring;
a second upper electrode formed over the gate of the block selecting transistor and being disconnected from the memory transistor, the first plug electrode, the block selecting transistor and the first wiring;
a second memory transistor formed on first semiconductor substrate, and having third and fourth impurity-diffused regions and a third gate;
a second plug electrode connected to the third impurity-diffused region;
a second lower electrode connected to the second plug electrode;
a second ferroelectric film formed on the second lower electrode;
a second wiring connected to the third impurity-diffused region of the second memory transistor;
a third upper electrode formed on the second ferroelectric film and being connected to the second wiring;
a fourth upper electrode formed over the gate of the second memory transistor and being disconnected from the second memory transistors, the second plug electrode, the block selecting transistor, the first wiring and the second wiring;
an insulating film formed over the semiconductor substrate, the first memory transistor, the second memory transistor, the first plug electrode, the second electrode, the first upper electrode, second upper electrode, the third upper electrode, fourth upper electrode, the first ferroelectric first the second ferroelectric film, the first lower electrode, and the second lower electrode.

14 more elements

A semiconductor memory device comprising:

a semiconductor substrate;
a memory cell block including a plurality of memory transistors formed on the semiconductor substrate the memory transistors having first and second impurity-diffused regions and a first gate formed between the first and second impurity-diffused regions and being connected in series, a plurality of memory cells connected in series each respectively having a first lower electrode connected to the first impurity diffused region, a first ferroelectric film formed on the lower electrode and a first upper electrode formed on the first ferroelectric film and being connected to the second impurity-diffused region;
an insulating layer formed on the semiconductor substrate and being adjoined to the first impurity-diffused region of the memory transistor located in one and of the memory cell block;
a block selecting circuit formed on the semiconductor substrate, and being adjoined to the insulating layer, and having a third impurity-diffused region, first fourth impurity diffused region and second gate;
and
a first conductive layer formed on the semiconductor substrate, and being connected to the lower electrode of the memory cell located in one end of the memory cell block and the third impurity-diffused region.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor device including dummy upper electrode

Life of this patent

Semiconductor device including dummy upper electrode

Life of this patent

Abstract

Claims29