Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells
AssigneeLSI Logic Corporation
InventorsWeidan Li, Benjamin Mbouombouo, Johann Leyrer
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Abstract
An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.
Claims16
An on-chip decoupling capacitor cell that is compatible with standard CMOS cells, comprising:
- a cell boundary defining an area of the cell, the area of the cell including a first transistor area and a second transistor area;
- a PMOS transistor formed within the first transistor area, the PMOS transistor including an n-well;
- and
- an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage and increased capacitance per unit area.
A method for reducing leakage of an on-chip decoupling capacitor cell that is compatible with neighboring standard CMOS cells, wherein adjacent cells are aligned such that NMOS areas of cells form a row, the method comprising the steps of:
- (a) providing the decoupling capacitor cell with a single PMOS transistor, wherein the PMOS transistor includes an n-well;
- and
- (b) extending the n-well into the NMOS area of cell, such that the extended n-well minimizes any impact on the neighboring standard CMOS cell.
A method for reducing leakage of an on-chip decoupling capacitor cell that is compatible with a neighboring standard CMOS cell, the standard CMOS cell including a PMOS transistor area and an NMOS transistor area, the method comprising the steps of:
- (a) providing the decoupling capacitor cell with a single PMOS transistor, wherein the PMOS transistor includes an n-well and at least one p-island formed in the n-well;
- and
- (b) extending the n-well and the at least one p-island into an area of the cell that is adjacent to the NMOS transistor area of the neighboring CMOS cell, such that the extended n-well and p-island minimize any impact on the neighboring standard CMOS cell.
Dependencies are inferred from the claim text.