Nonvolatile semiconductor memory array with skewed array arrangement

A semiconductor device comprising a memory cell array in which a plurality of nonvolatile semiconductor memory devices are arrayed in a row direction and a column direction,

• wherein each of the nonvolatile semiconductor memory devices includes:
• a semiconductor substrate;
• a floating gate disposed on the semiconductor substrate through a first insulating layer which is capable of functioning as a gate insulating layer interposed therebetween;
• a second insulating layer disposed on the floating gate;
• a third insulating layer which is formed in contact with at least part of the floating gate and is capable of functioning as a tunnel insulating layer;
• a control gate which is isolated from the floating gate by the third insulating layer and extends in the row direction;
• and
• impurity diffusion layers which are formed in the semiconductor substrate, forming a source region and a drain region,
• wherein the nonvolatile semiconductor memory devices which are adjacent to each other in the row direction are isolated by element isolations region extending in the column direction,
• wherein one of angles formed where a major axis direction of the floating gates in a planar configuration of the memory cell array intersects the column direction is an acute angle,
• wherein each of the element isolation regions is separately formed by every two rows of the nonvolatile semiconductor memory devices,
• wherein one impurity diffusion layer which forms the source region or the drain region is separate in the row direction by the element isolation region, and
• wherein the other impurity diffusion layer which forms the drain region or the source region is formed continuously in the row direction.