Apparatus for biasing ultra-low voltage logic circuits

An integrated circuit device comprising:

• a plurality of transistors;
• and
• a global body bias circuit having a first output and a second output, wherein each of said first output and said second output is connected to a corresponding one of said plurality of transistors, wherein said global body bias circuit includes a first transistor and second transistors connected in series between a first power supply and a second power supply, wherein a gate and a source of said first transistor are connected to said first power supply, wherein a gate and a source of said second transistor are connected to said second power supply, wherein drains and bodies of said first and second transistors are connected together for biasing bodies of a third transistor and a fourth transistor of said global body bias circuit, wherein gates of said third and said fourth transistors are connected to said first power supply and said second power supply, respectively.