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US 6,605,845 B1Granted
Asymmetric MOSFET using spacer gate technique
AssigneeIntel Corporation
InventorChunlin Liang
Life of this patent
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Abstract
A field effect transistor including a semiconductor substrate having a first doped region and a second doped region wherein the first doped region and the second doped region are defined by an implantation property. The implantation property of the first doped region has a first implantation characteristic and the implantation property of the second doped region has a second implantation characteristic, and the first implantation characteristic are different from the second implantation characteristic.
Claims11
A field effect transistor, comprising:
- a semiconductor substrate having a first doped region and a second doped region separated from said first doped region;
- and
- a gate electrode overlying a surface of said semiconductor substrate and dimensions of said gate electrode defining a symmetric channel region of said semiconductor substrate and having dimensions of a gate length and a gate height,
- said first doped region and said second doped region defined by an implantation property,
- said implantation property of said first doped region having a first implantation characteristic and said implantation property of said second doped region having a different second implantation characteristic,
- one of said first doped region and said second doped region substantially encroaches a first area of said symmetric channel region beneath said gate electrode, and
- the other of said first doped region and said second doped region encroaches a second area of said symmetric channel region beneath said gate electrode, the second area of encroachment being less than the first area of encroachment.
4 more elements
A transistor device comprising:
- a semiconductor substrate having a source region and a drain region separated from said source region by a symmetric channel region;
- and
- a gate electrode overlying a gate area of a surface of said semiconductor substrate over a portion of said symmetric channel region with dimensions comprising a substantially uniform gate length of less than 2000 Å and a height,
- wherein said symmetric channel region has a cross-sectional area defined between the source region and the drain region, and
- wherein the drain region encroaches said symmetric channel region and said source region substantially encroaches said symmetric channel region, the drain region encroachment being less than the source region encroachment.
2 more elements
Dependencies are inferred from the claim text.