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US 6,605,499 B1Granted
Method of forming sea-of-cells array of transistors
AssigneeHyundai Electronics America
InventorHarold S. Crafts
Life of this patent
Estimating the term…
Abstract
The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.
Claims10
A method of constructing an integrated circuit, comprising:
- configuring an n-channel field effect transistor;
- configuring a p-channel field effect transistor;
- configuring said n-channel field effect transistor and said p-channel field effect transistor so as to form a logic inverter;
- configuring a gate of the logic inverter from a layer of polysilicon;
- configuring a trace connecting a drain of the p-channel field effect transistor and a drain of the n-channel field effect transistor in said same layer of polysilicon, wherein said trace is substantially planar.
2 more elements
Dependencies are inferred from the claim text.