Process for optically erasing charge buildup during fabrication of an integrated circuit
AssigneeAxcelis Technologies, Inc.
InventorsAlan C. Janos, Anthony Sinnot, Ivan Berry, Kevin Stewart, Robert Douglas Mohondro
Life of this patent
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Abstract
A process for optically reducing charge build-up in an integrated circuit includes exposing the integrated circuit or portions thereof to a broadband radiation source. The process effectively reduces charge buildup that occurs in the manufacture of integrated circuits.
Claims21
A process for removing charge buildup during fabrication of an integrated circuit, the process comprising:
- exposing the integrated circuit to a broadband radiation pattern at an intensity and exposure time effective to reduce the charge buildup occurring during fabrication of the integrated circuit.
A process for reducing a charge buildup on a floating gate electrode during fabrication of an integrated circuit, the process comprising:
- placing the integrated circuit into a process chamber, wherein the integrated circuit comprises the floating gate electrode;
- and
- exposing the integrated circuit to a broadband radiation pattern at an intensity and exposure time effective to reduce the charge buildup on the floating gate electrode.
A process for removing a wavelength absorbing atmosphere, for wavelengths of about 180 nanometers to about 200 nanometers, in a charge erasure optical exposure tool, wherein the optical exposure tool includes a radiation source chamber in optical communication with a process chamber, the process comprising:
- purging the radiation source chamber with an inert gas substantially transparent to the wavelength absorbed by the ambient (pre-purged) atmosphere;
- and
- purging the process chamber with an inert gas substantially transparent to the wavelength absorbed by the ambient (pre-purged) atmosphere.
Dependencies are inferred from the claim text.