US 6,604,233 B1Granted

Method for optimizing the integrated circuit chip size for efficient manufacturing

AssigneeTexas Instruments Incorporated

InventorsCarl A. Vickery, James D. Goon, Robert A. Tuerck, Troy M. Loveday, Jesse Rojas

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Abstract

The number of good IC (Integrated Circuit) chips per wafer or time to print a wafer is optimized by examining a number of prospective chip-to-wafer offsets, and, for each offset, a number of prospective arrangements of reticle exposures (shot maps). Integrating such a shot map optimization sub-system with a reticle layout (frame generation) sub-system permits creation of an optimal shot map for an IC chip of known size. These two sub-systems can also be used iteratively to explore a range of possible chip sizes, presenting the results in a simple graphical form. The instant invention integrates shot map optimization, frame generation and chip size optimization/visualization into a single system, providing the chip designer with insight into the impact of chip size on manufacturability.

Claims6

Dependent claims

A method for determining an optimum shot map in a photolithographic process for a wafer surface, said method comprising the steps of:

defining a set of input parameters;
defining a circle with a diameter on said wafer surface;
constructing a chip matrix comprising a plurality of chips, each of said plurality of chips having a plurality of corners, and whereby said plurality of chips are arranged in a regular pattern in a x-y Cartesian coordinate plane;
generating a plurality of line segments formed by connecting said corners of any two chips in said plurality of chips such that each of said plurality of line segments has a length that is less than said diameter of said circle;
defining a plurality of chip-to-wafer offsets of said chip matrix and said wafer surface whereby each of said chip-to-wafer offsets is defined by a chord formed by one of said plurality of line segments and said circle;
determining a plurality of shot maps from said chip-to-wafer offsets and said set of input parameters;
and
determining an optimum shot map from said set of input parameters and said plurality of shot maps.

5 more elements

A method for determining an optimum chip size for integrated circuit manufacturing, said method comprising the steps of:

defining a set of designer parameters;
defining a set of reticle layout processes for a wafer fab;
defining a set of shot map processes for said wafer fab;
generating means for forming a chip size contour plot;
and
determining said optimum chip size from said contour plot and said set of designer parameters.

3 more elements

Dependencies are inferred from the claim text.