US 6,603,330 B1 · Configuring digital functions in a digital configurable macro architecture

Abstract

A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. The programmable digital circuit blocks can be configured to coupled in series or in parallel to handle more complex digital functions. More importantly, the configuration of the programmable digital circuit block is determined by its small number of configuration registers. This provides much flexibility. In particular, the configuration of the programmable digital circuit block is fast and easy since changes in configuration are accomplished by changing the contents of the configuration registers, whereas the contents are generally a small number of configuration data bits. Thus, the programmable digital circuit block is dynamically configurable from one predetermined digital function to another predetermined digital function for real-time processing.

Claims28

Dependent claims

A programmable digital circuit block comprising:

a system input for inputting a plurality of configuration data corresponding to any one of a plurality of predetermined digital functions;
a configuration register coupled to said system input for receiving and storing said configuration data and for configuring said programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data, wherein said configuration register is dynamically programmable with said configuration data;
a plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said programmable digital circuit block, wherein said configuration register configures and selects any of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said configuration data;
and
a data register coupled to said selectable logic circuits for storing data to facilitate performing any one of said plurality of predetermined digital functions.

2 more elements

A programmable digital device comprising:

an array of programmable digital circuit blocks, each programmable digital circuit block comprising:
a system input for inputting a plurality of configuration data corresponding to any one of a plurality of predetermined digital functions;
a configuration register coupled to said system input for receiving and storing said configuration data and for configuring said programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data, wherein said configuration register is dynamically programmable with said configuration data;
a plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said programmable digital circuit block, wherein said configuration register configures and selects any of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said configuration data;
and
a data register coupled to said selectable logic circuits for storing data to facilitate performing any one of said plurality of predetermined digital functions.

3 more elements

A controller apparatus comprising:

a programmable digital circuit block comprising:
a system input for inputting a plurality of configuration data corresponding to any one of a plurality of predetermined digital functions;
a configuration register coupled to said system input for receiving and storing said configuration data and for configuring said programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data, wherein said configuration register is dynamically programmable with said configuration data;
a plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said programmable digital circuit block, wherein said configuration register configures and selects any of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said configuration data;
and
a data register coupled to said selectable logic circuits for storing data to facilitate performing any one of said plurality of predetermined digital functions.

3 more elements

Dependencies are inferred from the claim text.

Configuring digital functions in a digital configurable macro architecture

Life of this patent

Configuring digital functions in a digital configurable macro architecture

Life of this patent

Abstract

Claims28