Container structure for floating gate memory device and method for forming same

A method for forming a floating gate memory device comprising:

• forming a first conductive floating gate layer;
• forming a second conductive floating gate layer comprising, in cross section, first and second vertically-oriented portions electrically coupled by a horizontally-oriented portion, wherein at least a portion of said horizontally-oriented portion is formed to overlie said first conductive floating gate layer, and further forming a recess defined by said vertically-oriented portions and said horizontally-oriented portion in said second polysilicon layer;
• and
• forming a conductive control gate layer at least partially within said recess in said second polysilicon layer.

A method used to form a semiconductor device comprising:

• providing a semiconductor wafer having a flat major surface oriented in a first direction;
• forming a tunnel oxide layer over said semiconductor wafer;
• forming a patterned first conductive floating gate layer generally oriented in said first direction and having a first thickness;
• forming a dielectric layer having a second thickness greater than said first thickness over said first floating gate layer;
• etching said dielectric layer to form first and second cross-sectional sidewalls in said dielectric layer and to expose said first conductive floating gate layer, wherein said sidewalls are generally oriented in a second direction generally perpendicular with said first direction;
• forming a second conductive floating gate layer comprising first and second portions generally oriented in said second direction which contact said first and second sidewalls respectively and a third portion generally oriented in said first direction which contacts said first and second portions, wherein said first, second, and third portions of said second floating gate layer define a recess therein;
• and
• forming a conductive control gate layer at least partially within said recess.

A method for forming a floating gate memory device comprising:

• forming a first conductive floating gate layer;
• forming a second conductive floating gate layer comprising, in cross section, first and second vertically-oriented portions electrically coupled by a horizontally-oriented portion, and further forming a recess defined by said vertically-oriented portions and said horizontally-oriented portion in said second polysilicon layer;
• and
• forming a conductive control gate layer at least partially within said recess in said second polysilicon layer such that said conductive control gate layer, in cross section, does not extend laterally beyond said second conductive floating gate layer.