Dual-gate CMOS semiconductor device manufacturing method
AssigneeOki Electric Industry Co., Ltd.
InventorHiroyuki Tanaka
Life of this patent
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Abstract
A manufacturing method for a dual-gate CMOS semiconductor device that suppresses mutual diffusion of P type impurities and N type impurities in a gate electrode. An NMOS part and a PMOS part are formed on a semiconductor substrate. A polycrystalline silicon layer is formed on the NMOS part and the PMOS part, and consists of an N type impurity containing polycrystalline silicon layer and a P type impurity containing polycrystalline silicon layer. A first conductive layer is formed on the polycrystalline silicon layer so as to include a groove region, in which the first conductive layer is not formed, on a predetermined region including a boundary between the N type impurity containing polycrystalline silicon layer and the P type impurity containing polycrystalline silicon layer.
Claims13
A dual-gate CMOS semiconductor device manufacturing method comprising:
- forming a P well and an N well on a semiconductor substrate using a first masking pattern;
- forming a gate insulating film on the P well and the N well;
- forming a polycrystalline silicon layer including a first polycrystalline silicon layer containing N type impurities and a second polycrystalline silicon layer containing P type impurities, on the gate insulating film;
- forming a first conductive layer on an entire surface of the first and second polycrystalline silicon layers;
- removing the first conductive layer on a predetermined region of the polycrystalline silicon layer including a boundary between the first polycrystalline silicon layer containing the N type impurities and the second polycrystalline silicon layer layer containing the P type impurities using a second masking pattern, to thereby form an opening exposing the upper surface of the polycrystalline silicon layer;
- forming a gate electrode by photolithography and etching;
- forming a source/drain layer on each of the P well and the N well by photolithography and ion implantation, after said forming a gate electrode;
- forming a metal suicide on surfaces of the first and second polycrystalline silicon layers at the opening;
- and
- depositing an insulating film on the first conductive layer, and on the metal silicide to fill the opening.
A dual-gate CMOS semiconductor device manufacturing method comprising:
- forming a P well and an N well on a semiconductor substrate using a first masking pattern;
- forming a gate insulating film on the P well and the N well;
- forming a polycrystalline silicon layer including a first polycrystalline silicon layer containing N type impurities and a second polycrystalline silicon layer containing P type impurities, on the gate insulating film;
- forming a first conductive layer on an entire surface of the first and second polycrystalline silicon layers;
- removing the first conductive layer on a predetermined region of the polycrystalline silicon layer including a boundary between the first polycrystalline silicon layer containing the N type impurities and the second polycrystalline silicon layer containing the P type impurities using a second masking pattern, to thereby form an opening exposing the upper surface of the polycrystalline silicon layer;
- forming a gate electrode by photolithography and etching;
- forming a source/drain layer on each of the P well and the N well by photolithography and ion implantation, after said forming a gate electrode;
- and
- embedding an insulating material in the opening of the first conductive layer so that the embedded insulating material is almost equal in height to the first conductive layer,
- the said embedding being between said removing the first conductive layer to form opening and said forming a gate electrode.
A dual-gate CMOS semiconductor device manufacturing method comprising:
- forming first and second wells on a semiconductor substrate;
- forming a gate insulating film on the first and second wells;
- forming a polycrystalline silicon layer on the gate insulating film, the polycrystalline silicon layer including a first polycrystalline silicon layer over the first well and a second polycrystalline silicon layer over the second well;
- forming a conductive layer on an entire surface of the first and second polycrystalline silicon layers;
- forming an opening in the conductive layer so as to expose a predetermined region of the upper surface of the polycrystalline silicon layer including a boundary between the first polycrystalline silicon layer and the second polycrystalline silicon layer;
- forming a metal silicide on surfaces of the first and second polycrystalline silicon layers within the opening;
- and
- depositing an insulating film on the conductive layer, and on the metal silicide to fill the opening.
Dependencies are inferred from the claim text.