Method of manufacturing alignment mark
AssigneeOki Electric Industry Co., Ltd.
InventorsSatoshi Machida, Akiyuki Minami
Life of this patent
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Abstract
A method for manufacturing a highly reliable alignment mark in which by-products do not form at an aligning mark position during patterning. In this method, an intermediate layer is disposed on an upper layer of a first wiring to protect the first wiring. Then, a filling material is coated thereon to fill in a through hole. Thereafter, a plug is formed by etch-backing, and a second wiring is formed.
Claims13
A method of manufacturing an alignment mark for aligning a pattern of a first pattern layer and a pattern of a second pattern layer in a predetermined layout when the first pattern layer and the second pattern layer are layered together on a wafer, comprising:
- forming a first alignment mark in a predetermined region of the first pattern layer during the formation of the first pattern layer;
- forming a second alignment mark by cutting the second pattern layer at a predetermined position thereof on the basis of the first alignment mark;
- providing a protective layer for protecting the second alignment mark;
- forming a predetermined pattern in a pattern forming region of the second pattern layer by using the first alignment mark;
- forming resist to a thickness at which the second alignment mark is filled in thereby;
- and
- removing the resist and exposing the second alignment mark after the predetermined pattern has been formed in the pattern forming region of the second pattern layer.
A method of manufacturing an alignment mark for aligning a pattern of a first pattern layer and a pattern of a second pattern layer in a predetermined layout when the first pattern layer and the second pattern layer are layered together on a wafer, comprising:
- forming a first alignment mark in a predetermined region of the first pattern layer during the formation of the first pattern layer;
- forming a second alignment mark by cutting the second pattern layer at a predetermined position thereof on the basis of the first alignment mark;
- providing a protective layer for protecting the second alignment mark;
- and
- forming a predetermined pattern in a pattern forming region of the second pattern layer by using the first alignment mark,
- wherein the protective layer is formed by a remaining portion of the second pattern layer when the second alignment mark is formed by cutting the second pattern layer.
A method of manufacturing an alignment mark for aligning a pattern of a first pattern layer and a pattern of a second pattern layer in a predetermined layout when the first pattern layer and the second pattern layer are layered together, comprising:
- forming a first alignment mark in a predetermined region of the first pattern layer during the formation of the first pattern layer;
- and
- by using the first alignment mark, forming a second alignment mark at a predetermined position of the second pattern layer and forming a predetermined pattern in a pattern forming region of the second pattern layer,
- wherein a feature size Wm of the second alignment mark and a feature size Wv of the predetermined pattern which is formed on the second pattern layer are determined to satisfy Wv<Wm<2×Wv.
A method of manufacturing an alignment mark for aligning a pattern of a first pattern layer and a pattern of a second pattern layer in a predetermined layout when the first pattern layer and the second pattern layer are layered together on a wafer, comprising:
- forming a first alignment mark in a predetermined region of the first pattern layer during the formation of the first pattern layer;
- forming a second alignment mark by cutting the second pattern layer at a predetermined position thereof on the basis of the first alignment mark;
- providing a protective layer for protecting the second alignment mark;
- and
- forming a predetermined pattern in a pattern forming region of the second pattern layer by using the first alignment mark,
- wherein the protective layer is formed by coating an insulating film material across the entire surface of the wafer, to a thickness at which the second alignment mark is not filled in by the material, and
- wherein a feature size Wm of the second alignment mark and a feature size Wv of the pattern of the second pattern layer are determined to satisfy Wv<Wm<2×WV, and the insulating film material is coated to substantially the same thickness as that of the feature size Wv.
Dependencies are inferred from the claim text.