System and method for generating a clock delay within an interconnect cable assembly

An apparatus for electrically connecting a data port of a first printed circuit board to a data port of a second printed circuit board and for electrically connecting a clock port of the first printed circuit board to a clock port of the second printed circuit board, the apparatus comprising:

• a data line electrically connected between the data port of the first printed circuit board and the data port of the second printed circuit board, the data line having a length;
• a first trace electrically connecting a data port of a driving integrated circuit with the data port of the first printed circuit board;
• a second trace electrically connecting a clock port of the driving integrated circuit with the clock port of the first printed circuit board;
• and
• a clock line electrically connected between the clock port of the first printed circuit board and the clock port of the second printed circuit board, the clock line having a length greater than the length of the data line such that a time delay is introduced into a clock signal transmitted on the clock line, thereby maximizing a data set up time and a data hold time of an associated data signal transmitted on the data line.

An apparatus for electrically connecting a data port of a first printed circuit board to a data port of a second printed circuit board and for electrically connecting a clock port of the first printed circuit board to a clock port of the second printed circuit board, the apparatus comprising:

• a data line electrically connected between the data port of the first printed circuit board and the data port of the second printed circuit board, the data line having a length;
• a clock line electrically connected between the clock port of the first printed circuit board and the clock port of the second printed circuit board, the clock line having a length greater than the length of the data line such that a time delay is introduced into a clock signal transmitted on the clock line, thereby maximizing a data set up time and a data hold time of an associated data signal transmitted on the data line;
• a first trace electrically connecting the data port of the second printed circuit board to a data port of a memory device;
• and
• a second trace electrically connecting the clock port of the second printed circuit board to a clock port of the memory device.

A method of passing a data signal between a driving integrated circuit in electrical connection with a first printed circuit board and an active edge sensitive clocking memory device in electrical connection with a second printed circuit board, the method comprising:

• providing a direct electrical connection between a data port of the driving integrated circuit and a data port of the memory device for a data signal;
• providing a delayed electrical connection between a clock port of the driving integrated circuit and a clock port of the memory device for a clock signal associated with the data signal, wherein the clock signal is time delayed between the first and second printed circuit boards;
• and
• capturing a stable data signal within the memory device when an active edge of an associated delayed clock signal is located at the clock port of the memory device.

A method of passing a data signal between a driving integrated circuit in electrical connection with a first printed circuit board and a memory device in electrical connection with a second printed circuit board, the method comprising:

• providing a direct electrical connection between a data port of the driving integrated circuit and a data port of the memory device for a data signal;
• providing a delayed electrical connection between a clock port of the driving integrated circuit and a clock port of the memory device for a clock signal associated with the data signal, wherein the clock signal is time delayed between the first and second printed circuit boards;
• transmitting a data signal between the first and second printed circuit boards via a data line having a length;
• transmitting a clock signal between the first and second printed circuit boards via a clock line having a length such that the length of the clock line is greater than the length of the data line;
• and
• capturing a stable data signal within the memory device when an associated delayed clock signal changes states at the clock port of the memory device.

A method of transmitting a data signal from a driving integrated circuit in electrical connection with a first printed circuit board to a memory device in electrical connection with a second printed circuit, the method comprising:

• transmitting a synchronized data signal and an associated clock signal to a data port and a clock port of the first printed circuit board;
• transmitting the data signal to a data port of the second printed circuit board;
• introducing a time delay in the clock signal during transmission of the clock signal to a clock port of the second printed circuit board, thereby creating a delayed clock signal;
• transmitting the data signal and the delayed clock signal to a data port and a clock port of the memory device in electrical connection with the second printed circuit board;
• and
• capturing a stable data signal within the memory device when an associated delayed clock signal changes states at the clock port of the memory device.