Integrated circuit bus grid having wires with pre-selected variable widths

A device, comprising:

• a semiconductor chip containing a plurality of cells and having at least one electrical bus designed using a current distribution modeled prior to arrangement of said plurality of cells, said semiconductor chip comprising:
• an area array of electrical contacts;
• and
• a plurality of regions defined by said area array, each of said plurality of regions containing a first metal layer having a plurality of first wires extending in a first direction and electrically coupled to said electrical contacts, each of said plurality of first wires having a first width;
• wherein said first widths of said first wires vary in each of said plurality of regions as a function of said current distribution;
• and
• a power supply in electrical communication with said semiconductor chip.

An integrated circuit, comprising:

• an area array of electrical contacts defining a plurality of contiguous rectangular regions each having a first axis of symmetry and a second axis of symmetry transverse to said first axis of symmetry;
• and
• an electrical bus grid formed within each of said contiguous rectangular regions, said repeatable electrical bus grid comprising:
• a first metal layer electrically connected to said electrical contacts;
• a plurality of first wires located in said first metal layer and extending parallel to said first axis of symmetry and spaced laterally from one another;
• wherein said plurality of first wires in each of said contiguous rectangular region have first widths that generally decrease in a direction toward said first axis of symmetry.