DRAM cell configuration whose memory cells can have transistors and capacitors with improved electrical properties

A method of producing a DRAM cell configuration, comprising;

• forming a first indentation and a second indentation in a substrate, with the first indentation and the second indentation laterally offset from one another;
• forming memory cells, each with a vertical transistor and a capacitor, and wherein the second indentation of a first memory cell adjoins the first indentation of an adjacent second memory cell and adjoins the substrate;
• forming transistors in the substrate, with a lower source/drain region, a channel region, and an upper source/drain region disposed one above the other;
• wherein the first indentation is formed in the substrate such that a first flank of the first indentation adjoins the lower source/drain region, the channel region, and the upper source/drain region;
• forming a capacitor dielectric of a capacitor in the first indentation;
• providing the capacitor dielectric with a recess on the first flank of the first indentation, in a region of the lower source/drain region;
• creating a memory node of the capacitor in the first indentation, wherein the node in the recess adjoins the lower source/drain region;
• wherein the second indentation is formed to adjoin the upper source/drain region, the channel region, and the lower source/drain region, and a bottom of the second indentation is located lower than a lower edge of the recess;
• forming a gate electrode of the transistor in the second indentation;
• creating a word line and a bit line extending transversely to the word line;
• and
• connecting the gate electrode of the transistor to the word line, and connecting the upper source/drain region to the bit line.