Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Shi Liu, Hui-Ling Wang, Szu-An Wu, Chun-Ching Tsan, Ying Lang Wang, Tong Hua Kuan
Estimating the term…
An improved composite dielectric structure and method of forming thereof which prevents delamination of FSG (F-doped SiO2) and allows FSG to be used as the interlevel dielectric between successive conducting interconnection patterns in multilevel integrated circuit structures has been developed. The composite dielectric structure comprises FSG, undoped silicon oxide (optional), silicon-rich silicon oxide and silicon nitride. The silicon-rich silicon oxide layer having a thickness between about 1000 and 2000 Angstroms prevents reaction of F atoms from the FSG layer with the silicon nitride layer during subsequent manufacturing heat treatment cycles and prevents the deleterious formation of delamination bubbles which cause peeling of the FSG layer.
A method of fabricating a multiple layer interlevel dielectric composite on a semiconductor substrate comprising the steps:
A method of fabricating a multiple layer interlevel dielectric composite on a semiconductor substrate comprising the steps:
An improved multiple layer interlevel dielectric composite structure for use between successive layers of conducting interconnection patterns on a semiconductor substrate, formed from a first dielectric layer comprising FSG deposited onto said semiconductor substrate, a second dielectric layer comprising undoped silicon oxide deposited by HDP deposition onto said first dielectric layer, a third dielectric layer comprising silicon-rich silicon oxide deposited by HDP deposition onto said second dielectric layer and a fourth dielectric layer comprising silicon nitride deposited by plasma enhanced deposition onto said third dielectric layer.
An improved multiple layer interlevel dielectric composite structure for use between successive layers of conducting interconnection patterns on a semiconductor substrate, formed from a first dielectric layer comprising FSG deposited onto said semiconductor substrate, a second dielectric layer comprising silicon-rich silicon oxide deposited by HDP deposition onto said first dielectric layer and a third dielectric layer comprising silicon nitride deposited by plasma enhanced deposition onto said second dielectric layer.
Dependencies are inferred from the claim text.