Method for forming metal silicide layer
AssigneeOki Electric Industry Co., Ltd.
InventorKaori Tai
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AssigneeOki Electric Industry Co., Ltd.
InventorKaori Tai
Estimating the term…
A method of forming a metal silicide layer with low resistance, with minimal consumption of silicon, includes depositing a first metal layer over a silicon-containing region, depositing a second metal layer over the first metal layer, forming an antioxidation layer over the second metal layer, and performing a first heat treatment on the structure to form a metal silicide preliminary layer from the silicon-containing region and the first metal layer and to form an alloy layer including a first metal and a second metal from the second metal layer and the first metal layer. The antioxidation layer and then the alloy layer and a portion of the remaining first metal layer are removed. A second heat treatment on the metal silicide preliminary layer at a higher temperature than the first heat treatment is performed, to change the metal silicide preliminary layer into a metal silicide layer.
A method for forming a metal silicide layer, comprising:
A method for forming a metal silicide layer, comprising:
A method for simultaneously forming metal silicide layers of different thickness over different silicon-containing regions, comprising:
A method for forming a metal suicide layer over a silicon-containing region, comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
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1. Field of the Invention
The present invention relates to a method for forming a metal silicide layer, and more particularly to a method for forming a cobalt silicide layer or a titanium silicide layer.
2. Description of Related Art
The foregoing and other objects, features and advantages of the present invention will be better understood from the following description taken in connection with the accompanying drawings, in which:
FIGS. 1(A) to 1(C) are process diagrams illustrating an embodiment of the present invention;
FIGS. 2(A) and 2(B) are process diagrams illustrating an embodiment of the present invention, and are a continuation of FIG. 1;
Embodiments of the present invention will now be described with reference to the figures. These figures are merely schematic illustrations of the shape, size, and arrangement relationships of the various components, and are intended to facilitate an understanding of the present invention, and therefore do not limit the present invention to the illustrated examples. In the figures, some of the hatching indicating cross sectional surfaces has been eliminated to make the figures easier to understand.
FIGS. 1A-1C and 2A-2B are simplified process diagrams illustrating an embodiment of the present invention. These figures are cross sections of the structure during formation.
The structure used in this embodiment has a silicon-containing region 12 formed as an island within an insulation region 10 such as an isolation region provided to a substrate (in this embodiment, the insulation region is encompassed by the term “substrate”).
Of FETs having insulated gates [IGFET]: using self-aligned silicidation
To Group IV semiconductors: using conductive layers comprising silicides
Semiconductor device manufacturing: process: temporary protective layer
Inorganic electric semiconductor devices
Term ended 24 Jan 2020 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.