Method of avoiding the effects of lack of uniformity in trench isolated integrated circuits
AssigneeSTMicroelectronics S.r.l.
InventorLuca Pividori
Life of this patent
Estimating the term…
Abstract
Method for fabricating integrated circuits comprising non-volatile memory cell matrices and peripheral circuits, said method comprising the steps of preparing a silicon substrate, carrying out a shallow trench isolation process on the silicon substrate to form active areas of exposed silicon isolated from one another by trenches filled with field oxide, growing a thin oxide layer on the active areas, masking the substrate areas intended for the memory cell matrices and etching the thin oxide layer and the field oxide by a chemical etch for a time longer than the time needed for removing the thin oxide layer entirely from the substrate areas intended for the peripheral circuits.
Claims11
A method for fabricating integrated circuits including non-volatile memory cell matrices and peripheral circuits, said method comprising the steps of:
- preparing a silicon substrate;
- carrying out a shallow trench isolation process on the silicon substrate to form active areas of exposed silicon isolated from one another by trenches filled with field oxide, the filled trenches having top surfaces with recesses formed in the field oxide;
- growing a thin silicon oxide layer on the active areas;
- masking substrate areas intended for the memory cell matrices;
- and
- etching the thin silicon oxide layer and the field oxide by a chemical etch for a time longer than a time needed for removing the thin silicon oxide layer entirely from the substrate areas intended for the peripheral circuits, to remove the recesses.
A method for fabricating integrated circuits comprising non-volatile memory cell matrices and peripheral circuits, said method comprising the steps of:
- preparing a silicon substrate;
- carrying out a shallow trench isolation process on the silicon substrate to obtain active areas of exposed silicon isolated from one another by trenches filled with field oxide, the filled trenches having top surfaces with recesses formed in the field oxide;
- growing a thin silicon oxide layer on the active areas;
- depositing a first layer of a conductive material;
- depositing a second layer of an insulating material;
- masking substrate areas intended for the memory cell matrices;
- removing the insulating material of said second layer and the conductive material of said first layer from unmasked areas to expose the thin silicon oxide layer and the field oxide of the substrate areas intended for the peripheral circuits;
- and
- etching the thin silicon oxide layer and the field oxide by a chemical etch for a time longer than a time needed for removing the thin silicon oxide layer entirely from the substrate areas intended for the peripheral circuits, to remove the recesses.
A method for fabricating integrated circuits including non-volatile memory cell matrices and peripheral circuits, said method comprising:
- carrying out a shallow trench isolation process on a silicon substrate to form active areas of exposed silicon isolated from one another by oxide plugs formed by trenches filled with field oxide, the oxide plugs having top surfaces with recesses formed in field oxide;
- growing a first thin dielectric layer on the active areas;
- masking substrate areas intended for the memory cell matrices;
- and
- overetching the thin dielectric layer and the field oxide by a chemical etch that removes the thin dielectric layer from substrate areas intended for the peripheral circuits and etches enough of the oxide plugs to remove the recesses, to where a level of at least some of the oxide plugs is lower than a level of adjacent active areas.
Dependencies are inferred from the claim text.