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US 6,586,301 B2Granted
Method of fabricating EEPROM having tunnel window area
AssigneeOki Electric Industry Co., Ltd.
InventorToshiyuki Orita
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Abstract
Heavily concentrated impurities are selectively introduced into a portion outside a polysilicon region of a region of a tunnel window area of an EEPROM memory cell, a polysilicon portion where impurities are not introduced is selectively etched, and then a tunnel oxide film is formed in a tunnel window area by oxidizing residual polysilicon.
Claims2
A method for fabricating an MOS transistor which includes a floating gate electrode and a thin film area for injection of a tunneling current into the floating electrode, comprising:
- forming a first oxide film and also a first polysilicon layer on a semiconductor substrate;
- selectively introducing BF2 ions to a polysilicon portion outside a region of the thin film area;
- selectively etching said polysilicon of the portion of the film where BF2 ions are not implanted;
- oxidizing all of said polysilicon that remains after said selectively etching;
- and
- forming polysilicon as a floating gate electrode in a portion including a region of the film.
3 more elements
Dependencies are inferred from the claim text.