Spacer assisted trench top isolation for vertical DRAM's

A method of manufacturing a vertical dynamic random access memory (DRAM) device, comprising:

• providing a workpiece, the workpiece including a substrate;
• forming a plurality of trenches in the workpiece, each trench having a top portion, a bottom portion, and sidewalls;
• forming a trench capacitor in each trench bottom portion, the trench capacitors having a top surface;
• disposing a first assist layer over at least the trench sidewalls and trench capacitor top surfaces;
• disposing a second assist layer over the first assist layer;
• removing the second assist layer from over at least the trench capacitor top surface;
• removing the first assist layer from at least the trench capacitor top surface using the second assist layer as a mask, leaving a portion of the workpiece at the trench sidewalls exposed proximate the trench capacitor top surface;
• removing the second assist layer;
• disposing a first insulating layer over at least the first assist layer and the trench capacitor top surface, the first insulating layer being conformal;
• disposing a second insulating layer over the first insulating layer;
• removing the second insulating layer from at least the trench sidewalls, leaving a portion of the second insulating layer over the trench capacitor top surface;
• and
• removing the first insulating layer and the first assist layer from the trench sidewalls, leaving a portion of the first insulating layer disposed over the trench capacitor top surface, wherein the remaining portions of the first and second insulating layer form a trench top isolation (TTI) layer of the vertical DRAM device.

A method of processing a semiconductor device that includes at least one trench formed within a workpiece, the trench comprising sidewalls, the method comprising:

• forming a first component within a bottom portion of the trench, leaving an upper portion of the trench exposed, the first component including a top surface;
• forming a first sacrificial oxide over at least the trench sidewalls and the first component top surface;
• disposing a first assist layer over the first sacrificial oxide, the first assist layer comprising a semiconductor material;
• disposing a second assist layer over the first assist layer, the second assist layer comprising an oxide;
• removing the second assist layer from at least over the first component top surface, leaving portions of the second assist layer remaining over the trench sidewalls;
• using the second assist layer as a mask to remove the first assist layer from at least over the first component top surface, leaving the first assist layer over at least a portion of the trench sidewalls;
• removing the second assist layer from the trench sidewalls;
• depositing a first insulating material over the first assist layer and the first component top surface, the first insulating material comprising a nitride;
• depositing a second insulating material over the first insulating material, the second insulating material comprising an oxide;
• removing the second insulating material from at least the trench sidewalls;
• and
• removing the first insulating material, and first assist layer from a top portion of the trench sidewalls, wherein the second insulating material and first insulating material remaining over the first component comprise a trench top isolation (TTI) layer.