US 6,586,291 B1 · High density memory with storage capacitor

Abstract

A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate. A transistor is formed having source and drain regions separated by a channel region, and a gate dielectric layer formed of the first deposited dielectric layer.

Claims12

Dependent claims

A method of concurrently forming a capacitor dielectric layer and a gate dielectric layer, the method comprising the steps of:

forming a mask on a (100) surface of a silicon substrate to expose a capacitor area,
cleaning the capacitor area of the surface of the silicon substrate,
etching the capacitor area with an etchant that preferentially etches the silicon substrate with a high degree of selectivity along (111) planes of the silicon substrate, thereby forming lower capacitor surfaces disposed at about fifty-five degrees from the surface of the silicon substrate with a self limiting etch that substantially stops when the capacitor surfaces are bounded by edges of the capacitor area and one another,
altering the silicon substrate in a portion disposed under the lower capacitor surfaces so as to be electrically conductive,
removing the mask from the surface of the silicon substrate,
concurrently forming a dielectric layer on the lower capacitor surfaces and on a channel area, where the dielectric layer on the lower capacitor surfaces is the capacitor dielectric layer and the dielectric layer on the channel area is the gate dielectric layer, and
forming a top capacitor plate of an electrically conductive material.

4 more elements

Dependencies are inferred from the claim text.

High density memory with storage capacitor

Life of this patent

High density memory with storage capacitor

Life of this patent

Abstract

Claims12