Simple photo development step to form TiSix gate in DRAM process

A method of fabricating an integrated circuit device comprising:

• forming field oxide areas on a semiconductor substrate surrounding and electrically isolating device areas, said device areas being a logic device area and a memory device area;
• providing polysilicon gate electrodes and associated source/drain regions in said device areas;
• forming silicon nitride spacers on the sidewalls of said polysilicon gate electrodes;
• depositing a silicon oxide layer overlying said polysilicon gate electrodes, said silicon nitride spacers, and said source/drain regions;
• covering said silicon oxide layer with a photoresist layer;
• developing away said photoresist layer until said silicon oxide layer overlying said polysilicon gate electrodes is exposed and remaining said photoresist layer is below the tops of said polysilicon gate electrodes;
• etching away said exposed silicon oxide layer whereby the tops of said polysilicon gate electrodes are exposed and wherein said silicon nitride spacers are protected by said remaining photoresist layer and thereby undamaged by said etching;
• removing said remaining photoresist layer;
• thereafter forming a photoresist mask covering said memory device area;
• etching away said all of silicon oxide layer not covered by said photoresist mask in said logic device area;
• removing said photoresist mask;
• thereafter depositing a layer of titanium over said semiconductor substrate;
• annealing said semiconductor substrate whereby said titanium layer is transformed into a titanium silicide layer over said gate electrodes and over said source/drain regions in said logic area not covered by said silicon oxide layer;
• and
• removing said titanium layer which is not transformed into titanium silicide overlying said spacers, said field oxide regions, and said silicon oxide layer to leave said titanium silicide layer only on the top surface of said gate electrodes and on the top surface of said semiconductor substrate overlying said source/drain regions associated with said gate electrodes in said logic device area to complete fabrication of said integrated circuit device.

A method of fabricating an integrated circuit device wherein a logic device area and a memory device area are fabricated on the same wafer comprising:

• forming field oxide areas on a semiconductor substrate surrounding and electrically isolating said device areas, said device areas being said logic device area and said memory device area;
• providing polysilicon gate electrodes and associated source/drain regions in said device areas;
• forming silicon nitride spacers on the sidewalls of said polysilicon gate electrodes;
• depositing a silicon oxide layer overlying said polysilicon gate electrodes, said silicon nitride spacers, and said source/drain regions;
• covering said silicon oxide layer with a photoresist layer;
• developing away said photoresist layer until said silicon oxide layer overlying said polysilicon gate electrodes is exposed and remaining said photoresist layer is below the tops of said polysilicon gate electrodes;
• etching away said exposed silicon oxide layer whereby the tops of said polysilicon gate electrodes are exposed wherein said etching step has a high selectivity for silicon oxide with respect to silicon nitride whereby said silicon nitride spacers are protected by said remaining photoresist layer and thereby undamaged by said etching;
• removing said remaining photoresist layer;
• thereafter forming a photoresist mask covering said memory device area;
• etching away said all of silicon oxide layer not covered by said photoresist mask in said logic device area;
• removing said photoresist mask;
• thereafter depositing a layer of titanium over said semiconductor substrate;
• annealing said semiconductor substrate whereby said titanium layer reacts with the polysilicon in said polysilicon gate electrodes and said silicon in said semiconductor substrate in said source/drain regions in said logic area not covered by said silicon oxide layer to form a titanium silicide layer and wherein said titanium layer overlying said spacers, said field oxide regions, and said silicon oxide layer is unreacted;
• and
• removing said unreacted titanium layer leaving said titanium silicide layer only on the top surface of said gate electrodes and on the top surface of said semiconductor substrate overlying said source/drain regions associated with said gate electrodes in said logic device area to complete fabrication of said integrated circuit device.