Multi-finger current ballasting ESD protection circuit and interleaved ballasting for ESD-sensitive circuits

A multi-finger ESD protection circuit, comprising:

• (a) first and second circuit terminals;
• (b) at least two resistive channels defining input fingers connected to the first circuit terminal;
• (c) at least first and second field effect transistors (FETs), each of the at least first and second FETs having a drain region, a source region and a gate electrode, the drain regions of the first and second FETs being connected to respective ones of the at least two resistive channels;
• (d) a first resistive element connected between the source region of the first FET and the second circuit terminal;
• (e) a second resistive element connected between the source region of the second FET and the second circuit terminal;
• and
• (f) a biasing transistor having source, gate and drain terminals, the source terminal of the biasing transistor being connected to the gate electrodes of the first and second FETs, the gate terminal of the biasing transistor being connected to the source region of the first FET and the drain terminal of the biasing transistor being connected to the first circuit terminal.

A multi-finger ESD protection circuit, comprising:

• (a) first and second circuit terminals;
• (b) a plurality of first resistive channels having first and second ends, the first ends of the plurality of first resistive channels being connected to the first circuit terminal, the plurality of first resistive channels defining a respective plurality of input fingers;
• (c) a plurality of field effect transistors (FETs), each of the plurality of field effect transistor having a drain, source and gate terminal, the gate terminals of the plurality of field effect transistors being connected together, the drain terminals of the plurality of field effect transistors being connected to the second ends of the plurality of input fingers, respectively;
• (d) a plurality of second resistive channels being connected between respective ones of the source terminals of the plurality of FETs and the second circuit terminal;
• (e) a plurality of biasing transistors, each having drain, source and gate terminals, the gate terminals of the plurality of biasing transistors being connected to the source terminals of the plurality of field effect transistors, respectively, the source terminals of the plurality of biasing transistors being connected to the second circuit terminal, and the drain terminals of the plurality of biasing transistors being connected together;
• (f) a further biasing transistor, having source, gate and drain terminals, the source terminal of the further biasing transistor being coupled to the first circuit terminal, the gate terminal of the further biasing transistor being coupled to the connected drain terminals of the plurality of biasing transistors and the drain terminal of the further biasing transistor being coupled to the connected gate terminals of the plurality of FETs;
• and
• (g) at least one resistor connected between the first circuit terminal and the connected drain terminals of the plurality of biasing transistors.

A multi-finger ESD protection circuit, comprising:

• (a) first and second circuit terminals;
• (b) at least two first resistive channels, connected at one end to the first circuit terminal, the at least two first resistive channels defining respective input fingers;
• (c) at least two field effect transistors (FETs), each of the at least two FETs having drain and source regions and a gate electrode, the drain regions of the at least two FETs being connected to respective ones of the at least two input fingers, the gate electrode of the at least two FETs being connected together;
• (d) at least two diodes, each having anode and cathode terminals, the anode terminal of each of the at least two diodes being connected to the source region of a respective one of the at least two FETs, the cathode terminals being connected to each other and to the connected gate electrodes;
• (e) at least one resistor connected between the second circuit terminal and the connected diode cathode terminals;
• and
• (f) at least two second resistive channels connected between respective ones of the source regions of the at least two FETs and the second circuit terminal.

A multi-finger ESD protection circuit for conducting ESD currents from a first circuit terminal to a second circuit terminal, comprising:

• (a) a triggering circuit for detecting an ESD event and producing a detection signal;
• (b) a transfer circuit responsive to the detection signal of the triggering circuit for producing a bias signal;
• and
• (c) a multi-finger turn-on transistor (MFT) circuit including a plurality of field effect transistors FETs, each FET having a drain electrode coupled to the first circuit terminal, a source electrode coupled to the second circuit terminal and a gate electrode, coupled to the gate electrodes of the plurality of FETs and coupled to receive the bias signal, the MFT circuit being responsive to the bias signal for channeling an electro-static discharge current through the plurality of FETs.

A multi-finger ESD protection circuit, comprising:

• first and second circuit terminals;
• at least first, second and third field effect transistors (FETs), each of FETs having a drain region, a source region and a gate electrode, the first, second and third FETs being configured such that the source regions of the first and second FETs are opposed and the drain regions of the second and third FETs are opposed;
• and
• a plurality of first resistive channels having first and second ends, the first ends being connected to the second circuit terminal and the second ends being coupled to the source regions of the first and second FETs, the plurality of first resistive channels being configured between the opposed source regions of the first and second FETs such that the first resistive channels coupled to the source region of the first FET are interleaved among the first resistive channels coupled to the source region of the second FET;
• and
• a plurality of second resistive channels having first and second ends, the first ends being connected to the first circuit terminal and the second ends being coupled to the drain regions of the second and third FETs, the plurality of second resistive channels being configured between the opposed drain regions of the second and third FETs such that the second resistive channels coupled to the drain region of the second FET are interleaved among the second resistive channels coupled to the drain region of the third FET.

A circuit for protecting a circuit terminal from an ESD event, comprising:

• a plurality of resistive elements having a first end and a second end, the first end being coupled to the circuit terminal;
• at least two transistor fingers, each of the at least two transistor fingers including a plurality of first electrodes, each of the first electrodes of each of the at least two transistor fingers being coupled to a respective first electrode of the other ones of the at least two transistor fingers and to the second end of a respectively different one of the plurality of resistive elements, and a plurality of second electrodes, each of the second electrodes being coupled to a source of reference potential;
• and
• means for interconnecting the plurality of transistor fingers, wherein, when a first one of the plurality of transistor fingers triggers, at least a second one of the plurality of transistor fingers is turned-on by a bias signal generated by the first one of the plurality of transistor fingers.

A circuit for protecting a circuit terminal from an ESD event, comprising:

• a plurality of resistive elements having a first end and a second end, the first end being coupled to a source of reference potential;
• at least two transistor fingers, each of the at least two transistor fingers including a plurality of first electrodes coupled to the circuit terminal and a plurality of second electrodes, each of the second electrodes of each of the at least two transistor fingers being coupled to a respective second electrode of the other ones of the at least two transistor fingers and to the second end of a respectively different one of the plurality of resistive elements;
• and
• means for interconnecting the plurality of transistor fingers, wherein, when a first one of the at least two transistor fingers triggers, at least a second one of the at least two transistor fingers is turned-on by a bias signal generated by the first one of the at least two transistor fingers.