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US 6,583,475 B2Granted
Semiconductor device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsChikao Makita, Kunihiko Karasawa
Life of this patent
Estimating the term…
Abstract
An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.
Claims15
A semiconductor device comprising:
- a p-type semiconductor substrate;
- an n-type semiconductor layer on the p-type semiconductor substrate;
- a p-type semiconductor layer on the n-type semiconductor layer;
- at least one NMOS transistor including, in the p-type semiconductor layer, a drain region, a source region, and a back gate region;
- a surge protection circuit having a first input impedance;
- an electrode pad to which both the drain region and the surge protection are connected;
- and
- an impedance adding unit having a second input impedance, higher than the first input impedance, that adds the second input impedance to the back gate region.
5 more elements
A semiconductor device comprising:
- a p-type semiconductor substrate;
- a first n-type semiconductor layer on the p-type semiconductor substrate;
- a second n-type semiconductor layer on the first n-type semiconductor layer;
- at least one PMOS transistor including, in the second n-type semiconductor layer, a drain region, a source region, and a back gate region;
- a surge protection circuit having a first input impedance;
- an electrode pad to which both the drain region and the surge protection are connected;
- and
- an impedance adding unit having a second input impedance, higher than the first input impedance, that adds the second input impedance to the back gate region.
5 more elements
A semiconductor device comprising:
- a p-type semiconductor substrate;
- a first n-type semiconductor layer on the p-type semiconductor substrate;
- a second n-type semiconductor layer and a p-type semiconductor layer, both on the first n-type semiconductor layer;
- at least one NMOS transistor including, in the p-type semiconductor layer, an n-type source region, and a p-type back gate region;
- a first surge protection circuit having a first input impedance;
- a first electrode pad to which both the n-type drain region and the first surge protection circuit are connected;
- a first impedance adding unit having a second input impedance, higher than the first input impedance, that adds the second input impedance to the p-type back gate region;
- at least one PMOS transistor including, in the second n-type semiconductor layer, a p-type drain region, a p-type source region, and an n-type back gate region;
- a second surge protection circuit having a third input impedance;
- a second electrode pad to which both the p-type drain region and the second surge protection circuit are connected;
- and
- a second impedance adding unit having a fourth input impedance, higher than the third input impedance, that adds the fourth input impedance to the n-type back gate region.
9 more elements
Dependencies are inferred from the claim text.