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US 6,583,458 B1Granted
Semiconductor integrated circuit including a DRAM and an analog circuit
AssigneeFujitsu Limited
InventorsMasao Hayashi, Taiji Ema, Narumi Ohkawa
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation film includes, in the first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of the interlayer insulation film in the second region.
Claims32
A semiconductor device, comprising:
- a substrate including a first region and a second region;
- an interlayer insulation film formed over said substrate so as to cover said first and second regions;
- and
- a capacitor formed over said interlayer insulation film in said first region;
- wherein said interlayer insulation film includes a groove having a bottom surface lower in level than a surface of said interlayer insulation film in said first region and said second region;
- said capacitor making a contact with said interlayer insulation film,
- said groove being formed at a boundary between said first and second regions and filled with an insulation layer.
4 more elements
A semiconductor device, comprising:
- a substrate having a diffusion region;
- an interlayer insulation film formed over said substrate;
- a first contact hole formed in said interlayer insulation film so as to expose said diffusion region;
- a side wall oxide film covering a side wall of said first contact hole;
- an electrode pattern formed over said interlayer insulation film so as to cover said first contact hole in such a state that said side wall oxide film is interposed between said electrode pattern and said side wall of said first contact hole;
- a first capacitor electrode formed over said substrate so as to be covered by said interlayer insulation film;
- a second contact hole formed in said interlayer insulation film so as to expose said first capacitor electrode;
- a capacitor insulation film formed over said interlayer insulation film so as to cover said second contact hole in conformity with a shape of said second contact hole, said capacitor insulation film having a composition substantially identical with a composition of said side wall oxide film;
- and
- a second capacitor electrode formed over said capacitor insulation film so as to cover said second contact hole via said capacitor insulation film, said first capacitor electrode, said second capacitor electrode and said capacitor insulation film forming together a capacitor.
7 more elements
A semiconductor device, comprising:
- a substrate defined with a memory cell region and a peripheral region;
- a memory cell transistor formed on said memory cell region of said substrate, said memory cell transistor constituting a memory cell;
- a first interlayer insulation film formed over said substrate so as to cover said memory cell region and said peripheral region continuously;
- a second interlayer insulation film formed over said first interlayer insulation film so as to cover said memory cell region and said peripheral region continuously;
- a first contact hole formed in a part of said first interlayer insulation film covering said memory cell region, said first contact hole providing an electrical connection to a first diffusion region of said memory cell transistor;
- a first side wall insulation film covering a side wall of said first contact hole;
- a first electrode formed over a part of said first interlayer insulation film covering said memory cell region such that said first electrode covers said first contact hole via said first side wall insulation film, said first electrode being covered by said second interlayer insulation film and making an electrical contact with said first diffusion region;
- a second contact hole formed over a part of said second interlayer insulation film covering said memory cell region so as to penetrate through said first interlayer insulation film, said second contact hole providing an electrical connection to a second diffusion region of said memory cell transistor;
- a second side wall insulation film covering a side wall of said second contact hole;
- a second electrode formed over a part of said second interlayer insulation film covering said memory cell region so as to cover said second contact hole, said second electrode making an electrical contact with said second diffusion region and constituting an accumulation electrode of a memory cell capacitor;
- a capacitor dielectric film covering said second electrode;
- an opposing electrode of said memory cell capacitor covering said second electrode via said capacitor insulation film;
- a device isolation film formed over said substrate in correspondence to said peripheral circuit region;
- a lower capacitor electrode formed over said device isolation region, said lower capacitor electrode being covered by said first interlayer insulation film;
- a third contact hole formed in a part of said first interlayer insulation film covering said lower capacitor electrode so as to expose said lower capacitor electrode;
- a capacitor insulation film formed over a part of said first interlayer insulation film covering said peripheral region so as to cover said third contact hole, said capacitor insulation film forming a depression in conformity in shape with a shape of said third contact hole;
- and
- a third electrode formed over said capacitor insulation film so as to cover said depression thereof, said third electrode constituting an upper capacitor electrode;
- said second interlayer insulation film including, in said memory cell region, a step defined by a groove having a bottom surface at a level lower than a level of a surface of said second interlayer insulation film in said peripheral region, said groove extending along a boundary between said memory cell region and said peripheral region;
- said lower capacitor electrode having a composition and a thickness substantially identical with those of a gate electrode of said memory cell transistor;
- said capacitor insulation film having a composition substantially identical with a composition of said first side wall insulation film,
- said third electrode having a composition and a thickness substantially identical with those of said first electrode.
19 more elements
A semiconductor device, comprising:
- a substrate defined with a memory cell region and a peripheral region;
- a memory cell transistor formed on said memory cell region of said substrate, said memory cell transistor constituting a memory cell;
- a first interlayer insulation film formed over said substrate so as to cover said memory cell region and said peripheral region continuously;
- a second interlayer insulation film formed over said first interlayer insulation film so as to cover said memory cell region and said peripheral region continuously;
- a first contact hole formed in a part of said first interlayer insulation film covering said memory cell region, said first contact hole providing an electrical connection to a first diffusion region of said memory cell transistor;
- a first side wall insulation film covering a side wall of said first contact hole;
- a first electrode formed over a part of said first interlayer insulation film covering said memory cell region so as to cover said first contact hole, said first electrode being covered by said second interlayer insulation film and making an electrical contact with said first diffusion region;
- a second contact hole formed over a part of said second interlayer insulation film covering said memory cell region, said second contact hole providing an electrical connection to a second diffusion region of said memory cell transistor;
- a second side wall insulation film covering a side wall of said second contact hole;
- a second electrode formed over a part of said second interlayer insulation film covering said memory cell region so as to cover said second contact hole, said second electrode making an electrical connection with said second diffusion region and constituting an accumulation electrode of a memory cell capacitor;
- a capacitor dielectric film covering said second electrode;
- an opposing electrode of said memory cell capacitor covering said second electrode via said capacitor dielectric film;
- a device isolation film formed over said substrate in correspondence to said peripheral region;
- a lower capacitor electrode formed over said device isolation film, said lower capacitor electrode being covered by said first and second interlayer insulation films;
- a third contact hole formed in a part of said first and second interlayer insulation films covering said peripheral region so as to expose said lower capacitor electrode;
- a capacitor insulation film formed in a part of said second interlayer insulation film covering said peripheral region so as to cover said third contact hole, said capacitor insulation film forming a depression in conformity with a shape of said third contact hole;
- and
- a third electrode formed over said capacitor insulation film so as to cover said depression, said third electrode constituting an upper capacitor electrode;
- said second interlayer insulation film including, in said memory cell region, a stepped part defined by a groove having a bottom surface lower in level than a top surface of said second interlayer insulation film in said peripheral region, said groove extending along a boundary between said memory cell region and said peripheral region;
- said lower capacitor electrode having a composition and a thickness substantially identical with those of a gate electrode of said memory cell transistor;
- said capacitor insulation film having a composition substantially identical with a composition of said first side wall insulation film;
- said third electrode having a composition and a thickness substantially identical with those of said second electrode.
19 more elements
A semiconductor device, comprising:
- a substrate defined with a memory cell region and a peripheral region;
- a memory cell transistor formed in said memory cell region of said substrate, said memory cell transistor constituting a memory cell;
- a first interlayer insulation film formed over said substrate so as to cover said memory cell region and said peripheral region continuously;
- a second interlayer insulation film formed over said first interlayer insulation film so as to cover said memory cell region and said peripheral region continuously;
- a first contact hole formed in a part of said first interlayer insulation film covering said memory cell region, said first contact hole providing an electrical connection to a first diffusion region of said memory cell transistor;
- a first side wall insulation film covering a side wall of said first contact hole;
- a first electrode formed over a part of said interlayer insulation film covering said memory cell region so as to cover said first contact hole, said first electrode being covered by said second interlayer insulation film and making an electrical connection with said first diffusion region;
- a second contact hole formed in a part of said second interlayer insulation film, said second contact hole providing an electrical connection to a second diffusion region of said memory cell transistor;
- a second side wall insulation film covering a side wall of said second contact hole;
- a second electrode formed over a part of said second interlayer insulation film covering said memory cell region so as to cover said second contact hole, said second electrode making an electrical contact with said second diffusion region and constituting an accumulation electrode of a memory cell capacitor;
- a capacitor dielectric film covering said second electrode;
- an opposing electrode of said memory cell capacitor covering said second electrode via said capacitor dielectric film;
- a third diffusion region formed in said peripheral region of said substrate, said third diffusion region being covered by said first and second interlayer insulation films;
- a third contact hole formed in a part of said first and second interlayer insulation films covering said peripheral region, said third contact hole providing an electrical contact with said third diffusion region;
- a capacitor insulation film formed over a part of said second interlayer insulation film covering said peripheral region so as to cover said third contact hole, said capacitor insulation film forming a depression in conformity with a shape of said third contact hole;
- and
- a third electrode formed over said capacitor insulation film so as to cover said depression, said third electrode constituting an upper capacitor electrode;
- said second interlayer insulation region including, in said memory cell region, a stepped part defined by a groove having a bottom surface at a level lower than a level of a surface of said second interlayer insulation film in said peripheral region, said groove extending along a boundary between said memory cell region and said peripheral region;
- said lower capacitor electrode having a composition and a thickness substantially identical with those of a gate electrode of said memory cell transistor;
- said capacitor electrode having a composition substantially identical with a composition of said first side wall insulation film;
- said third electrode having a composition and a thickness substantially identical with those of said second electrode.
18 more elements
A semiconductor device, comprising:
- a substrate;
- a first conductive layer formed over said substrate;
- an interlayer insulation film formed over said substrate so as to cover said first conductive layer;
- a contact hole formed in said interlayer insulation film so as to expose said substrate;
- a side wall insulation film covering a side wall of said contact hole;
- a conductive side wall film covering aside wall of said side wall insulation film;
- and
- a second conductive layer covering said conductive side wall film in said contact hole, said second conductive layer making an electrical contact with a surface of said substrate,
- said conductive side wall film having a sleeve form conformal to said side wall of said contact hole.
6 more elements
A semiconductor integrated circuit, comprising:
- a substrate;
- a first semiconductor device formed on a first region of said substrate;
- a second semiconductor device formed on a second region of said substrate;
- an interlayer insulation film formed over said substrate;
- a first opening formed in a part of said interlayer insulation film covering said first region;
- a first electrode covering said first opening;
- a second opening formed in a part of said interlayer insulation film covering said second region;
- a second electrode covering said second opening;
- an insulation film covering said interlayer insulation film;
- and
- a third electrode formed over said insulation film in correspondence to said first electrode so as to sandwich said insulation film between said first electrode and said third electrode;
- said first electrode filling said first opening but limited to inside of said first opening;
- said second electrode filling said second opening but limited to inside of said second opening.
10 more elements
A semiconductor integrated circuit, comprising:
- a substrate;
- a first semiconductor device formed on a first region of said substrate;
- a second semiconductor device formed on a second region of said substrate;
- a first electrode formed over said first region of said substrate;
- a first insulation film covering said first electrode;
- a plurality of second electrodes formed in said second region of said substrate, each of said second electrodes comprising a side wall covered by a second insulation film, a pair of said plurality of second electrodes thereby forming a self-aligned contact hole therebetween;
- a third electrode formed over said first insulation film so as to sandwich said first insulation film between said first electrode and said third electrode to form an analog capacitor device constituting a circuit element;
- and
- a fourth electrode covering said self-aligned contact hole;
- said third electrode and said fourth electrode having a substantially identical composition.
7 more elements
A semiconductor integrated circuit, comprising:
- a substrate;
- a first semiconductor device formed on a first region of said substrate;
- a second semiconductor device formed on a second region of said substrate;
- a first gate electrode formed over said first region of said substrate;
- a plurality of second gate electrodes formed over said second region of said substrate, each of said second gate electrodes comprising a side wall covered by a second insulation film, a pair of said plurality of second gate electrodes forming a self-aligned contact hole therebetween;
- an interconnection electrode covering said self-aligned contact hole;
- said first gate electrode and said second gate electrode having different compositions.
4 more elements
A semiconductor integrated circuit, comprising:
- a substrate;
- a first semiconductor device formed on a first region of said substrate;
- a second semiconductor device formed on a second region of said substrate;
- an interlayer insulation film formed over said substrate;
- a first opening formed in a part of said interlayer insulation film covering said first region;
- a first electrode covering said first opening;
- a second opening formed in a part of said interlayer insulation film covering said second region;
- a second electrode covering said second opening;
- an insulation film covering said interlayer insulation film;
- and
- a third electrode formed over said insulation film in correspondence to said first electrode so as to sandwich said insulation film between said first electrode and said third electrode;
- said first electrode and said second electrode having respective top surfaces located at an identical level as measured from a surface of said substrate,
- said second electrode acting as an interconnection element connecting said second semiconductor device to a conductor provided on said insulation film.
10 more elements
Dependencies are inferred from the claim text.