Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry

A semiconductor processing method of making an electrical interconnect between an electrically conductive line and a substrate node location comprising:

• forming a first dielectric layer over a substrate, the first dielectric layer having an outer surface overlying a substrate node location;
• forming a first line layer overlying the outer dielectric surface and the substrate node location;
• forming a second dielectric layer over the first line layer and patterning the second dielectric layer to expose portions of the first line layer, one exposed portion of the first line layer being adjacent the substrate node location;
• forming a second line layer over the first line layer and the patterned second dielectric layer;
• etching the first and second line layers to form an interconnect line having an outer portion and an inner portion, and to expose the substrate node location, wherein (1) the second line layer comprises the outer portion of the line and has an outer portion terminus disposed over the inner portion, and (2) the first line layer comprises the inner portion of the line and which extends laterally outward relative to the outer portion and having an inner portion terminus adjacent the node location;
• forming an insulating material over the line and the exposed substrate node location;
• etching the insulating material effective to form a sidewall spacer over at least most of an exposed edge of the outer portion terminus and to remove at least some of the second dielectric layer over the laterally extending inner portion to expose at least some of the first line layer;
• and
• forming a refractory metal layer over the exposed first line layer and the exposed substrate node location.