Innovative narrow gate formation for floating gate flash technology

A method of forming a stacked gate flash memory cell, comprising:

• forming a tunnel oxide layer, a floating gate polysilicon layer, an oxide-nitride-oxide layer, and a control gate polysilicon layer in succession over a semiconductor substrate;
• forming an oxide sacrificial layer over the control gate polysilicon layer;
• patterning an antireflective coating layer over the oxide sacrificial layer;
• patterning the antireflective coating layer to form an antireflective coating feature having at least one lateral sidewall edge associated therewith;
• forming a polysilicon spacer layer over the antireflective coating feature;
• patterning the polysilicon spacer layer, thereby removing the spacer layer in a portion overlying the antireflective coating feature and in a portion overlying an exposed portion of the oxide sacrificial layer, and leaving a portion of the polysilicon spacer against the lateral sidewall edge of the antireflective coating layer, thereby defining a polysilicon sidewall spacer having a width associated therewith;
• removing the antireflective coating feature;
• patterning the oxide sacrificial layer using the spacer as a hard mask, thereby defining an oxide sacrificial hard mask structure underlying the spacer;
• and
• patterning the control gate polysilicon layer, the oxide-nitride-oxide layer and the floating gate polysilicon layer using the polysilicon spacer and the oxide sacrificial hard mask structure as a hard mask, thereby defining the stacked gate, wherein a width of the stacked gate is a function of the spacer width.