ESD protection scheme for outputs with resistor loading
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJian-Hsing Lee, Shui-Hun Chen, Jiaw-Ren Shih
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Abstract
Disclosed are structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD) by preventing ESD current from flowing through resistive means between that output pad and an internal circuit. By splitting the active region and thereby creating a bipolar transistor which connects directly to the output pad, the resistive means is shunted when the bipolar transistor together with an already existing parasitic bipolar transistor conduct during ESD. Current flow in the resistive means is therefore eliminated and with it damaging power dissipation.
Claims3
A method for protecting from electrostatic discharge (ESD) the output of an integrated circuit with resistor loading, comprising the steps of:
- a) providing a first MOS transistor of a first conductivity type in a region of a second conductivity type of a semiconductor substrate;
- b) splitting the drain of said first MOS transistor into two regions adjacent to each other, thereby creating two parasitic diodes and two parasitic bipolar transistors;
- c) providing a second MOS transistor of a second conductivity type in a region of a first conductivity type in the semiconductor substrate;
- d) splitting the drain of said second MOS transistor into two regions adjacent to each other, thereby creating two parasitic diodes;
- e) coupling the drain which is adjacent to the gate of each of said MOS transistors, via a resistive means, to an output pad;
- and
- f) connecting the other drain of each of said MOS transistors to said output pad.
Dependencies are inferred from the claim text.