Method of controlling the deposition of inter-level dielectric layers based upon electrical performance tests, and system for accomplishing same

A method, comprising:

• performing at least one electrical performance test on an integrated circuit device;
• determining, based upon data obtained from said at least one electrical performance test, a target thickness of at least one inter-level dielectric layer to be formed above a wafer by accessing a model that correlates data obtained from said at least one electrical performance test with a target thickness for said at least one inter-level dielectric layer;
• and
• performing a deposition process to form said at least one inter-level dielectric layer to said target thickness above said wafer.

A method, comprising:

• performing at least one electrical performance test on at least one integrated circuit device comprised of a plurality of inter-level dielectric layers, each having a plurality of conductive interconnections formed therein;
• determining, based upon data obtained from said at least one electrical performance test, a target thickness of at least one inter-level dielectric layer to be formed above a subsequently processed wafer;
• and
• performing a deposition process to form said at least one inter-level dielectric layer to said target thickness above said wafer.

A method, comprising:

• performing at least one electrical performance test on at least one integrated circuit device;
• determining, based upon data obtained from said at least one electrical performance test, a duration of a deposition process to be performed to form at least one inter-level dielectric layer above a wafer;
• and
• performing said deposition process for said determined duration to form said at least one inter-level dielectric layer above said wafer.

A method, comprising:

• performing at least one electrical performance test on at least one integrated circuit device;
• determining, based upon data obtained from said at least one electrical performance test, a duration of a deposition process to be performed to form at least one inter-level dielectric layer above a wafer by accessing a model that correlates data obtained from said at least one electrical performance test with a duration of said deposition process to be performed to form said at least one inter-level dielectric layer;
• and
• performing said deposition process for said determined duration to form said at least one inter-level dielectric layer above said wafer.

A method, comprising:

• performing at least one electrical performance test on at least one integrated circuit device comprised of a plurality of inter-level dielectric layers, each having a plurality of conductive interconnections formed therein;
• determining, based upon data obtained from said at least one electrical performance test, a duration of a deposition process to be performed to form at least one inter-level dielectric layer above a subsequently processed wafer;
• and
• performing said deposition process for said determined duration to form said at least one inter-level dielectric layer above said wafer.

A system, comprising:

• an electrical metrology tool adapted to perform at least one electrical test on at least one integrated circuit device;
• a controller that determines, based upon data obtained from said at least one electrical performance test, a target thickness of at least one inter-level dielectric layer to be formed above a wafer;
• and
• a deposition tool for performing a deposition process to form said at least one inter-level dielectric layer to said target thickness.

A system, comprising:

• an electrical metrology tool adapted to perform at least one electrical test on an integrated circuit device;
• a controller that determines, based upon data obtained from said at least one electrical performance test, a duration of a deposition process to be performed to form at least one inter-level dielectric layer;
• and
• a deposition tool for performing said deposition process for said determined duration.

A system, comprising:

• means for performing at least one electrical test on at least one integrated circuit device;
• a controller means for determining, based upon data obtained from said at least one electrical performance test, a target thickness of at least one inter-level dielectric layer to be formed above a wafer;
• and
• means for performing said deposition process to form said at least one inter-level dielectric layer to said target thickness.

A system, comprising:

• means for performing at least one electrical test on at least one integrated circuit device;
• a controller means for determining, based upon data obtained from said at least one electrical performance test, a duration of a deposition process to be performed to form at least one inter-level dielectric layer above a wafer;
• and
• means for performing said deposition process for said determined duration.