Low-voltage-triggered SOI-SCR device and associated ESD protection circuit

A silicon-on-insulator (SOI) silicon controlled rectifier (SCR) device structure, comprising:

• a substrate;
• an insulation layer above the substrate;
• a plurality of isolation structure above the insulation layer such that a device region is formed between the isolation structures,
• a first-type well and a second-type well, wherein the first and the second-type wells are connected and formed in the device region;
• a first gate structure formed in the first-type well;
• a second gate structure formed in the second-type well;
• a first second-type doped region formed in the first-type well adjacent to the first gate structure;
• a first first-type doped region formed in the first-type well between the first second-type doped region and the isolation structure adjacent to the first second-type doped region, wherein the first second-type doped region and the first first-type doped region are electrically connected to form a cathode of the SOI-SCR device;
• a second second-type doped region formed in the first-type and the second-type well around a junction between the first and second-type wells between the first and the second gate structure;
• a second first-type doped region formed in the second well;
• a third second-type doped region formed in the second-type well between the second first-type doped region and the isolation structure adjacent to the second first-type doped region, wherein the second first-type doped region and the third second-type doped region are electrically connected to form an anode of the SOI-SCR device;
• and
• a fourth second-type doped region formed in the second well between the second first-type doped region and the second gate structure adjacent to the second first-type doped region.

A silicon-on-insulator (SOI) silicon controlled rectifier (SCR) device structure, comprising:

• a substrate;
• an insulation layer above the substrate;
• a plurality of isolation structure above the insulation layer such that a device region is formed between the isolation structures;
• a first-type well and a second-type well, wherein the first and the second-type wells are connected and formed in the device region;
• a first gate structure formed above the first-type well;
• a second gate structure formed above the second-type well;
• a first first-type doped region formed in the first-type well adjacent to a portion of a sidewall of the first gate structure;
• a first second-type doped region formed within a portion of the first-type well adjacent to the first first-type doped region;
• a second first-type doped region formed in the device region between the first second-type doped region and the isolation structure adjacent to the first-type well, wherein the first second-type doped region and the second first-type doped region are electrically connected to form a cathode of the SOI-SCR device;
• a third first-type doped region formed within the second-type well and the second-type well around a junction of the first and second-type wells between a portion of sidewalls between the first and the second gate structure;
• a second second-type doped region formed in the device region adjacent to the second-type well;
• and
• a fourth first-type doped region formed within a portion of the second-type well between the second second-type doped region and a portion of a sidewall of the second gate structure, wherein the second second-type doped region and the fourth first-type doped region are electrically connected to form an anode of the SOI-SCR device.

A silicon-on-insulator (SOI) silicon controlled rectifier (SCR) device structure, comprising:

• a substrate;
• an insulation layer above the substrate;
• a plurality of isolation structure above the insulation layer such that a device region is formed between the isolation structures;
• a first-type well and a second-type well, wherein the first and the second-type wells are connected and formed in the device region;
• a first gate structure formed above the first-type well;
• a second gate structure formed above the second-type well;
• a first second-type doped region formed in the first-type well adjacent to a portion of a sidewall of the first gate structure;
• a first first-type doped region formed in the device region between the first second-type doped region and the isolation structure adjacent to the first second-type doped region, wherein the first second-type doped region and the first first-type doped region are electrically connected to form a cathode of the SOI-SCR device;
• a second second-type doped region formed between a portion of the first and the second-type well around a junction of the first and second-type wells between a portion of sidewalls of the first and the second gate structure;
• a third second-type doped region formed within a portion of the second-type well adjacent to a portion of the sidewall of the second gate structure;
• a second first-type doped region formed within a portion of the second-type well adjacent to the third second-type doped region;
• and
• a fourth second-type doped region formed in the device region between the second first-type doped region and another isolation structure adjacent to the second-type well, wherein the second first-type doped region and the fourth second-type doped region are electrically connected to form an anode of the SOI-SCR device.