Memory storage cell based array of counters

An apparatus, comprising:

• a counter array having a plurality of counters, each counter of the plurality of counters having a memory cell, each memory cell coupled to a bit line and a complement bit line;
• an address decoder coupled to the counter array to select at least one of the memory cells within the counter array;
• and
• read/write circuitry coupled to the counter array to pass data with the counter array over the bit lines and the complementary bit lines, and wherein each counter comprises:
• a first flop;
• and
• a second flop coupled to the first flop, each of the first and second flops comprising:
• a master latch having a first one of the memory cells and a first set/reset circuit;
• and
• a slave latch coupled to the master latch, the slave latch having a second one of the memory cell and a second set/reset circuit, and wherein each of the master and slave latches comprise:
• a first transistor coupled to the memory cell, the first transistor having a gate coupled to receive a set signal to set the memory cell and a first terminal coupled to the bit line of the memory cell;
• a second transistor coupled to the memory cell, the second transistor having a gate coupled to receive a reset signal to reset the memory cell and a first terminal coupled to the complement bit line of the memory cell;
• and
• a third transistor coupled to the first and second transistors to enable the memory cell, the first transistor having a second terminal coupled to the
• third transistor, the second transistor having a second
• terminal coupled to the third transistor.

An apparatus, comprising:

• first and second flip-flops each having first and second latches, the first and second latches each having a data input, a clock input, and a data output, wherein each of the first and second latches comprises:
• a memory cell having a bit line;
• first, second, and third transistors each having a gate terminal and first channel terminal and a second channel terminal, the first channel terminals of the first and second transistors coupled to the bit line, the first channel terminal of the third transistor coupled to the second channel terminals of the first and second transistors;
• and
• a first inverter having an input and an output, the output of the first inverter coupled to the gate terminal of the first transistor and the input of the first inverter coupled to the gate terminal of the second transistor, and
• wherein the bit line of the memory cell of the first latch is coupled to the input of the first inverter of the second latch, the bit line of the memory cell of the second latch is coupled to an input of a second inverter, an output of the second inverter coupled to the input of the first inverter.

A method, comprising:

• receiving a data value at an input to a first logic circuit;
• storing the data value in a first memory cell;
• providing the data value to a second memory cell coupled to the first memory cell through a second logic circuit;
• outputting the data value from the second memory cell;
• and
• feeding back one of the output data value from the second memory cell and an
• inverted output data value from the second memory cell to the input of the first logic circuit.