Back to results
US 6,566,926 B1Granted
Hysteretic self-biased amplifier
AssigneeIntel Corporation
InventorJames D. Patterson
Life of this patent
Estimating the term…
Abstract
An amplifier and system includes hysteresis circuits.
Claims29
A circuit comprising:
- a first differential pair of input transistors coupled between a pair of output nodes and a first common node, the first differential pair of input transistors having control nodes coupled between a pair of input nodes;
- a second differential pair of input transistors coupled between the pair of output nodes and a second common node, the second differential pair of input transistors having control nodes coupled between the pair of input nodes;
- a first tail transistor coupled between the first common node and an upper voltage supply node;
- a second tail transistor coupled between the second common node and a lower voltage supply node, wherein the first and second tail transistors are configured to be biased by one of the pair of output nodes;
- an output sense hysteresis tuning circuit coupled between the pair of output nodes;
- and
- an output switch hysteresis circuit coupled between the pair of output nodes.
4 more elements
A self-biased amplifier circuit comprising:
- a first tail transistor coupled to be biased by a first amplifier output node, the first tail transistor coupled to an upper voltage supply node;
- a second tail transistor coupled to be biased by the first amplifier output node, the second tail transistor coupled to a lower voltage supply node;
- an output sense hysteresis tuning circuit coupled between the first and second tail transistors, the output sense hysteresis tuning circuit configured to drive the first amplifier output node in response to a second amplifier output node;
- and
- an output switch hysteresis circuit coupled between the first and second tail transistors, the output switch hysteresis circuit configured to drive the second amplifier output node in response to the first amplifier output node.
2 more elements
An apparatus comprising:
- first and second tail transistors;
- a hysteresis circuit;
- a first feedback transistor coupled between the first tail transistor and the hysteresis circuit;
- a second feedback transistor coupled between the second tail transistor and the hysteresis circuit;
- and
- a feedback circuit to couple a control node of the first feedback transistor to an upper voltage supply node through a first diode, and to couple a control node of the second feedback transistor to a lower voltage supply node through a second diode.
3 more elements
A system comprising:
- a first tail transistor coupled to be biased by a first amplifier output node, the first tail transistor coupled to an upper voltage supply node;
- a second tail transistor coupled to be biased by the first amplifier output node, the second tail transistor coupled to a lower voltage supply node;
- an output sense hysteresis tuning circuit coupled between the first and second tail transistors, the output sense hysteresis tuning configured to drive the first amplifier output node in response to a second amplifier output node;
- an output switch hysteresis circuit coupled between the first and second tail transistors, the output switch hysteresis circuit configured to drive the second amplifier output node in response to the first amplifier output node;
- and
- a universal serial bus controller coupled to the second amplifier output node.
3 more elements
Dependencies are inferred from the claim text.