Layout design method
AssigneeNEC Electronics Corporation
InventorsFutoshi Nagayoshi, Shoichiro Sato
Life of this patent
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Abstract
A method for designing routes for multilevel interconnections in a semiconductor device having at least a field effect transistor having a gate electrode, where the route extends between a diffusion region and the gate electrode. Each interconnection connected to the gate electrode is given an area which does not exceed a predetermined antenna effect reference value by inserting a buffer, such as a logic gate, into the interconnection on the same level as the interconnection.
Claims10
A semiconductor device having at least a field effect transistor having a gate electrode and at least a route comprising multilevel interconnections, and said route extending between a diffusion region and the gate electrode,
- wherein each interconnection has an area which does not exceed a predetermined reference value, provided that said each interconnection is connected to said gate electrode without intervening any higher level inter-layer contact and any higher level interconnection than said each interconnection and further without intervening any buffer, and that said each interconnection is connected to said diffusion region through a buffer.
A method of designing a layout for a semiconductor device that has a diffusion area connected to a gate electrode of a field effect transistor, the method designing a route for an interconnector between the diffusion area and the gate electrode and comprising the steps of:
- determining whether the interconnector has an area that exceeds an antenna effect reference value;
- and
- when the interconnect has an area that exceeds the antenna effect reference value, adding a buffer to the interconnect to divide the interconnect so that a first portion of the divided interconnect contacting the gate electrode has an area that is less than the antenna effect reference value.
A computer program for designing a layout for a semiconductor device that has a diffusion area connected to a gate electrode of a field effect transistor, the program designing a route for an interconnector between the diffusion area and the gate electrode and performing the steps of:
- determining whether the interconnector has an area that exceeds an antenna effect reference value;
- and
- when the interconnect has an area that exceeds the antenna effect reference value, adding a buffer to the interconnect to divide the interconnect so that a first portion of the divided interconnect contacting the gate electrode has an area that is less than the antenna effect reference value.
A semiconductor device comprising:
- a diffusion area connected to a gate electrode of a field effect transistor by an interconnector that extends between the diffusion area and the gate electrode;
- said interconnector having a first portion at a first level that is connected to said gate electrode, said first portion having an area that does not exceed an antenna effect reference value, said interconnector also having a second portion connected to said diffusion area;
- a buffer at said first level connecting said first portion to said second portion.
Dependencies are inferred from the claim text.