Compensation circuit for leakage through electrostatic discharge protection devices

An integrated circuit, comprising:

• a reference voltage generator circuit, for generating a reference voltage;
• functional circuitry, for performing a circuit function responsive to a voltage corresponding to the reference voltage;
• a series resistor connected between the reference voltage generator circuit and an external terminal;
• an ESD protection circuit, connected to the external terminal;
• and
• an ESD compensation circuit, connected to the external terminal, and comprising:
• a dummy ESD cell, constructed to match the characteristics of the ESD protection circuit;
• and
• a first current mirror, having a first leg connected between a first voltage and the ESD protection circuit, and having a second leg connected between the first voltage and the dummy ESD cell, the first and second legs of the first current mirror arranged to conduct equivalent currents, the first current mirror comprises:
• a first MOS transistor of a first conductivity type, having a source-drain path connected on one end to the first voltage, and having a gate;
• a second MOS transistor of a second conductivity type, having a source-drain path coupled on one end to the source-drain path of the first MOS transistor in the first leg of the first current mirror, and coupled on another end to the ESD protection circuit, and having a gate connected to its drain;
• a third MOS transistor of the first conductivity type, having a source-drain path connected on one end to the first voltage, and having a gate connected to the gate of the first MOS transistor;
• and
• a fourth MOS transistor of the second conductivity type, having a source-drain path coupled on one end to the source-drain path of the third MOS transistor in the second leg of the first current mirror, and coupled on another end to the dummy ESD cell, and having a gate connected to the gate of the second MOS transistor.

A method of generating a filtered reference voltage for use in an integrated circuit, comprising:

• generating a reference voltage for use by functional circuitry;
• generating an initialization signal for use by an ESD compensation circuit;
• applying the reference voltage to a low-pass filter comprised of a series resistor and an off-chip capacitor, having a node therebetween at an external terminal of the integrated circuit, at which an ESD cell is connected for the protection of the functional circuitry from electrostatic discharge energy;
• applying the initialization signal to the ESD compensation circuit;
• and
• balancing leakage current drawn by the ESD cell at the external terminal by conducting current through a second leg of a current mirror, the second leg of the current mirror connected to a dummy ESD cell, within said ESD compensation circuit, having matched characteristics with the ESD cell, and symmetrically biased with a first leg of the current mirror that is connected to the ESD cell.

A method of generating a filtered reference voltage for use in an integrated circuit, comprising:

• generating a reference voltage for use by functional circuitry;
• applying the reference voltage to a low-pass filter comprised of a series resistor and an off-chip capacitor, having a node therebetween at an external terminal of the integrated circuit, at which an ESD cell is connected for the protection of the functional circuitry from electrostatic discharge energy;
• balancing leakage current drawn by the ESD cell at the external terminal by conducting current through a second leg of a current mirror, the second leg of the current mirror connected to a dummy ESD cell having matched characteristics with the ESD cell, and symmetrically biased with a first leg of the current mirror that is connected to the ESD cell;
• and
• initializing conduction in the second leg of the current mirror upon startup of the integrated circuit.

A method of generating a filtered reference voltage for use in an integrated circuit, comprising:

• generating a reference voltage for use by functional circuitry;
• applying the reference voltage to a low-pass filter comprised of a series resistor and an off-chip capacitor, having a node therebetween at an external terminal of the integrated circuit, at which an ESD cell is connected for the protection of the functional circuitry from electrostatic discharge energy;
• and
• balancing leakage current drawn by the ESD cell at the external terminal by conducting current through a second leg of a current mirror, the second leg of the current mirror connected to a dummy ESD cell having matched characteristics with the ESD cell, and symmetrically biased with a first leg of the current mirror that is connected to the ESD cell wherein the integrated circuit includes first and second current mirrors, each having a first leg connected to the ESD cell and a second leg connected to the dummy ESD cell, the first and second current mirrors biased by first and second voltages, respectively;
• and wherein the balancing step utilizes a selected one of the first and second current mirrors responsive to the polarity of the leakage current drawn by the ESD cell.