Voltage tolerance ESD protection circuit
AssigneeWinbond Electronics Corp.
InventorWei-Fan Chen
Life of this patent
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Abstract
The present invention provides an ESD protection circuit for preventing an internal circuit from being damaged by ESD, wherein the internal circuit is connected to a pad. The ESD protection circuit comprises a first transistor, a second transistor and a voltage divider. The first transistor has a drain connected to the pad. The second transistor has a source and a gate both connected to an input node for a supply voltage, and has a drain connected to a source of the first transistor. The voltage divider is connected between the pad and the input node for the supply voltage, and also connected to a gate of the first transistor for providing a bias voltage thereto when ESD occurs.
Claims9
An ESD protection circuit for preventing an internal circuit from being damaged by ESD, wherein the internal circuit is connected to a pad, the ESD protection circuit comprising:
- a first transistor having a drain connected to the pad and through which ESD flows when the pad suffers ESD;
- a second transistor having a source and gate both connected to an input node for a supply voltage and having a drain coupled to a source of the first transistor;
- and
- a voltage divider connected between the pad and the input node for the supply voltage, comprising an upper load and an lower load connected in series, the upper load and lower load also being coupled to the pad and the input node for the supply voltage respectively, and the gate of the first transistor being connected to where the upper load and lower load are connected together for receiving a bias voltage when ESD occurs.
Dependencies are inferred from the claim text.