Mask ROM cell and method of fabricating the same
AssigneeLG Semicon Co., Ltd.
InventorJin Soo Kim
Life of this patent
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Abstract
Mask ROM cell and method of fabricating the same, is disclosed, including a semiconductor substrate of a first conductivity type, a plurality of impurity diffusion regions of a second conductivity type, formed in the semiconductor substrate in one direction, having a predetermined distance therebetween, an insulating layer formed on a portion of the semiconductor substrate, corresponding to each impurity diffusion region, a gate insulating layer formed on only a portion of the semiconductor substrate, between the impurity diffusion regions and a plurality of conductive lines formed on the gate insulating layer and insulating layer in a predetermined interval, being perpendicular to the impurity diffusion regions.
Claims7
A mask ROM cell, comprising:
- a plurality of impurity diffusion regions of a second conductivity type, formed in a surface of a semiconductor substrate in one direction, having a predetermined distance and free of other impurity diffusion regions therebetween;
- an insulating layer formed completely above the surface of the semiconductor substrate and entirely covering a portion of the semiconductor substrate surface corresponding to each impurity diffusion region;
- another insulating layer formed only on a portion of the semiconductor substrate between the impurity diffusion regions, whereby the other insulating layer is a gate insulating layer;
- and
- a plurality of conductive lines formed on and in contact with both the gate insulating layer and the insulating layer in a predetermined interval, being perpendicular to the impurity diffusion regions.
A mask ROM cell, comprising:
- a plurality of impurity diffusion regions, formed in a surface of a semiconductor substrate in one direction, having a distance and free of other impurity diffusion regions therebetween;
- a first insulating layer formed completely above the surface of the semiconductor substrate, the first insulating layer entirely covering a portion of the semiconductor substrate surface corresponding to each impurity diffusion region and being absent over a portion of the semiconductor substrate surface corresponding to a gate region;
- a second insulating layer formed on the gate region between the impurity diffusion regions as a gate insulating layer;
- and
- a plurality of conductive lines formed on and in contact with both the gate insulating layer and the first insulating layer.
Dependencies are inferred from the claim text.