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US 6,555,874 B1Granted
Method of fabricating high performance SiGe heterojunction bipolar transistor BiCMOS on a silicon-on-insulator substrate
AssigneeSharp Laboratories of America, Inc.
InventorsSheng Teng Hsu, Douglas James Tweet, Bruce Dale Ulrich, Hong Ying
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Abstract
A semiconductor structure includes, on a SOI substrate, a CMOS formed on the substrate; and a SiGe HBT formed on the substrate. A method of fabricating a semiconductor structure includes preparing a SOI substrate having plural active regions thereon; forming a CMOS on the SOI substrate in a first active region; and forming a SiGe HBT on the SOI substrate in another active region.
Claims12
A semiconductor structure comprising:
- a SOI substrate;
- a CMOS formed on the substrate and isolated from other structures formed on the substrate;
- and
- a SiGe HBT formed on the substrate, substantially isolated from other structures formed on the substrate which includes a collector buried in the SOI substrate below the depth of the insulating layer thereof, wherein said SiGe HBT includes a germanium-doped silicon layer having a bas-collector interface and a base-emitter interface, and wherein a germanium concentration decreases monotonically from a range of between about 15% to 20% at the base-collector interface to a concentration of less than about 5% at the base emitter interface.
1 more element
A method of fabricating a semiconductor structure comprising:
- preparing a SOI substrate;
- forming a CMOS on said substrate;
- and
- forming a SiGe HBT on said substrate, including fabricating a collector and a collector contact, wherein the collector contact is buried in the SOI substrate below the depth of the insulating layer thereof, which includes providing a germanium-doped silicon layer having a base-collector interface and a base-emitter interface, and wherein a germanium concentration decreases monotonically from a range of between about 15% to 20% at the base-collector interface to a concentration of less than about 5% at the base emitter interface.
1 more element
A method of fabricating a semiconductor structure comprising:
- preparing a SOI substrate having plural active regions therein and a top silicon layer thereon;
- forming a CMOS on said substrate in a first active region;
- isolating the CNMOS Tom other structures on the substrate with oxide to reduce parasitic capacitance;
- and
- forming a SiGe HBT on said substrate in another active region, including fabricating a collector and a collector contact, wherein the collector contact is buried in the SOI substrate below the depth of the insulating layer thereof, and wherein the remainder of the SiGe HBT is isolated from other structures on the substrate by oxide, and which includes providing a germanium-doped silicon layer having a base-collector interface and a base-emitter interface, and wherein a germanium concentration decreases monotonically from a range of between about 15% to 20% at the base-collector interface to a concentration of less than about 5% at the base emitter interface.
2 more elements
Dependencies are inferred from the claim text.