Stacked local interconnect structure and method of fabricating same
AssigneeMicron Technology, Inc.
InventorJigish D. Trivedi
Life of this patent
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Abstract
A method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device for economizing space available within the IC device and increasing design flexibility. In one embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.
Claims3
A protection method for features of a semiconductor device during manufacturing operations preventing damage due from inadvertent etching, comprising:
- providing a semiconductor substrate including a plurality of device features;
- forming a passivation layer over portions of said semiconductor substrate;
- forming an interlayer dielectric over said passivation layer;
- selecting one or more device features to be protected from said inadvertent etching during said manufacturing operations;
- and
- providing a metallization layer over said one or more device features for protection thereof.
A protection method for portions of a semiconductor device preventing inadvertent damage from etching during manufacturing operations, said etching, comprising:
- providing a semiconductor substrate including a plurality of device features on said portions thereof;
- forming a passivation layer over said portions of said semiconductor substrate;
- forming an interlayer dielectric over said passivation layer;
- selecting one or more device features to be protected from said inadvertent etching during said manufacturing operations;
- and
- providing a metallization layer over said one or more device features for protection thereof.
A protection method for portions of at least one semiconductor device on a wafer preventing inadvertent damage from etching during manufacturing operations, said etching, comprising:
- providing at least one semiconductor device on a wafer including a plurality of device features on said portions thereof;
- forming a passivation layer over said portions of said semiconductor device on said wafer;
- forming an interlayer dielectric over said passivation layer;
- selecting one or more device features to be protected from said inadvertent etching during said manufacturing operations;
- and
- providing a metallization layer over said one or more device features for protection thereof.
Dependencies are inferred from the claim text.