Method of manufacture of a crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor

A process comprising steps in the sequence as follows:

• forming a sublayer of a conductor layer in contact with a plurality of conductive plugs formed in a planarizing glass insulating layer which covers gate electrode/conductor stacks with spacers, with the conductive plugs in direct contact with the spacers, by the sequence as follows:
• forming a stack of silicon dioxide layers which are alternatingly doped and undoped on the conductive sublayer with the stack comprising a bottom layer formed on top of the conductive sublayer and each additional layer in the stack formed on a previous one of the layers in the stack including an undoped top silicon dioxide layer on top of the stack, with the doped silicon dioxide layers comprising BPSG layers,
• forming a mask over the stack with mask openings therethrough,
• etching the silicon dioxide layers through the mask openings to form capacitor-core-shaping cavities in the stack of silicon dioxide layers reaching down through the stack to the conductive sublayer at the bottom of the stack,
• differentially etching the silicon dioxide layers in the cavities with a combination of hydrogen fluoride vapor and water vapor forming undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stack into the cavities to complete the plurality of molds,
• depositing a thick conductive layer into the cavities to form monolithic, solid capacitor cores with counterpart cantilevered ribs with a complementary pattern to the plurality of molds and the capacitor cores having inner cavities and a top surface, each of the monolithic, solid capacitor cores being formed of a material selected from the group consisting of aluminum, copper, tungsten, and titanium nitride and each of the monolithic, solid capacitor cores having a thickness from 500 Å to 1,000 Å,
• polishing away the undoped top silicon dioxide layer of the plurality of molds and the top surface of each of the monolithic, solid capacitor cores by a Chemical Mechanical Planarization (CMP) process which removes the top undoped layer of the plurality of molds and the top of each of the monolithic, solid capacitor cores providing a flat upper surface thereof with a rib located on top of each of the monolithic, solid capacitor cores,
• etching away the plurality of molds, and
• then, after etching away the plurality of molds, etching back the sub layer to separate the thin, monolithic capacitor cores from adjacent thin, monolithic capacitor cores exposing the planarizing glass insulating layer.