Process flow for capacitance enhancement in a DRAM trench

A method of forming a deep trench structure having increased surface area comprising the steps of:

• (a) forming a deep trench in a semiconductor substrate, said deep trench having an upper region, a lower region and interior walls;
• (b) forming a collar stack in said upper region of said deep trench;
• (c) forming a discontinuous polysilicon layer on exposed interior walls of the lower trench region, said discontinuous polysilicon layer having gaps therein which expose portions of said substrate;
• (d) oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with said discontinuous polysilicon layer;
• and
• (e) etching said oxide material and any remaining discontinuous polysilicon layer so as to form smooth hemispherical grooves on the walls of the trench region which are substantially free of polysilicon.