Non-volatile semiconductor memory device and manufacturing method thereof

A non-volatile semiconductor memory device comprising:

• a semiconductor substrate;
• an isolation insulating film, provided on the semiconductor substrate, for defining a plurality of device forming regions continuous in one direction at a predetermined interval;
• and
• a memory cell array constructed of a plurality of memory cells arranged in array on the semiconductor substrate and each including a charge-storage layer provided via a first gate insulating film on the device forming region, and a control gate disposed in such a direction as to traverse the isolation insulating film via a second gate insulating film on the charge-storage layer and extending continuously astride of the plurality of memory cells,
• wherein the charge-storage layer of the memory cell is provided in pattern so that a part of the charge-storage layer is superposed on the isolation insulating film from above the device forming region, and
• a protective insulating film covered with the second gate insulating film and a control gate is disposed on the isolation insulating film interposed between the device forming regions adjacently to the charge-storage layer.

A non-volatile semiconductor memory device comprising a cell array of a plurality of memory cells connected to each other, each memory cell including:

• a plurality of trenches aligned on a semiconductor substrate in one direction;
• an isolation region in which an isolation insulating film is buried in each trench;
• a plurality of semiconductor regions electrically isolated by the isolation region;
• a charge-storage layer formed on each semiconductor region via a first gate insulating film;
• and
• a control gate formed on the charge-storage layer via a second gate insulating film,
• wherein the charge-storage layer is a stacked layer of two or more conductive layers, a side end portion of the lowest conductive layer of the conductive layers being located to meet a wall of each trench, the highest conductive layer having the same width as or being wider than the lowest conductive layer, and the upper surface of the isolation insulating film being flush with the upper surface of the highest conductive layer of the charge-storage layer.

A non-volatile semiconductor memory device comprising a cell array of a plurality of memory cells connected to each other, each memory cell including:

• a plurality of trenches aligned on a semiconductor substrate in one direction;
• an isolation region in which an isolation insulating film is buried in each trench;
• a plurality of semiconductor regions electrically isolated by the isolation region;
• a charge-storage layer formed on each semiconductor regions via a first gate insulating film;
• and
• a control gate formed on the charge-storage layer via a second gate insulating film,
• wherein the charge-storage layer is a stacked layer of two or more conductive layers, a side end portion of the lowest conductive layer of the conductive layers being located to meet a side wall of each trench, the highest conductive layer having the same width as or being wider than the lowest conductive layer, and the upper surface of the isolation insulating film being located between the lower surface and the upper surface of the highest conductive layer of the charge-storage layer.

A non-volatile semiconductor memory device comprising a cell array of a plurality of memory cells connected to each other, each memory cell including:

• a plurality of isolation region in which an isolation insulating film is buried in each of trenches aligned in one direction on a semiconductor substrate;
• a plurality of semiconductor regions electrically isolated by the isolation regions;
• charge-storage layers each formed on respective semiconductor region via a first gate insulating film, each charge-storage layer having two or more conductive layers stacked each other;
• and
• a control gate formed on the charge-storage layer via a second gate insulating film,
• wherein the semiconductor memory device has a relationship Y>X1>X2 or Y>X1=X2 where X1 denotes a distance between side end portions of the isolation regions adjacent to each other, Y denotes a distance between side end portions of the lowest layers of the charge-storage layers adjacent to each other and X2 denotes a distance between side end portions of the highest layers of the adjacent charge-storage layers.