Output buffer with improved ESD protection

An output buffer, comprising:

• a pull-high circuit connected between a relatively-high power node and an IC pad;
• and
• a pull-low circuit connected between a relatively-low power node and the IC pad, the pull-low circuit having a resistance modulator and an ESD protection-device connected in series;
• wherein the resistance modulator comprises a resistor and a rectifying circuit connected in parallel and the rectifying circuit comprises a plurality of diodes of a first polarity connected in series;
• the resistance modulator provides a first resistance during circuit operation, and provides a second resistance lower than the first resistance during an ESD event.

An output buffer, comprising:

• a pull-high circuit connected between a relatively-high power node and an IC pad;
• and
• a pull-low circuit connected between a relatively-low power node and the IC pad, the pull-low circuit having a resistance modulator and an ESD protection device connected in series;
• wherein the resistance modulator comprises a resistor and a rectifying circuit connected in parallel and the rectifying circuit comprises a first diode of a first polarity and a second diode of a second polarity connected in parallel;
• the resistance modulator provides a first resistance during circuit operation, and provides a second resistance lower than the first resistance during an ESD event.

An electrostatic discharge (ESD) protection buffer wherein said buffer is formed on a semiconductor substrate and connected between an integrated circuit input pad and a power node, said ESD protection buffer comprising:

• a transistor and
• a resistance modulator connected in series with said transistor,
• said resistance modulator comprising:
• a first-type semiconductor substrate;
• a second-type well region formed within said semiconductor substrate;
• a first-type doped region formed within said well region;
• a first second-type doped region formed within said well region and electrically connected to said first-type doped region formed within said well region;
• and
• a second second-type doped region at least partially formed within said well region;
• and said transistor comprising a finger-shaped NMOS or PMOS transistor with a plurality of interlaced source and drain regions disposed within said semiconductor substrate, wherein said resistance modulator has a first resistance to suppress voltage ringing and overshooting when said integrated circuit pad is sending or receiving a signal and said resistance modulator has a second resistance lower than the first resistance when an ESD event is present at said integrated circuit pad.