Bond pads using mesh pattern via structures for protecting devices/circuits under I/O pads

A vertical structure and a method of forming a vertical structure, comprising:

• providing a partially processed semiconductor wafer having completed ESD structures, including a topmost interlevel dielectric layer through which metallic vias are formed for electrical connection;
• forming a first metal level with at least one ESD structure disposed, at least partially, under said first metal level;
• forming an IMD level by forming a blanket dielectric layer over said first metal level, patterning and etching said dielectric layer to form mesh patterns of trenches passing through said dielectric layer, filling said trenches with a conducting material, and performing CMP, which results in a structure that prevents cracking of the IMD;
• forming n metal level, IMD level pairs, where n is an integer greater than or equal to zero;
• depositing bonding metal patterns;
• bonding wires onto said bonding metal patterns;
• forming a passivation layer.

A bonding pad structure and a method of forming a bonding pad that is immune to IMD cracking and protects underlying areas from damaging stresses, comprising:

• forming a first metal level over a topmost IDL;
• forming an IMD level by forming a blanket dielectric layer over said first metal level, patterning and etching said dielectric layer to form mesh patterns of trenches passing through said dielectric layer, filling said trenches with a conducting material, and performing CMP, which results in a structure that prevents cracking of the IMD;
• forming n metal level-IMD level pairs, where n is an integer greater than or equal to zero;
• depositing bonding metal patterns;
• bonding wires onto said bonding metal patterns;
• forming a passivation layer.