Power MOS transistor having increased drain current path

The power MOS transistor comprising:

• a substrate of a first conductivity type;
• a well region of a second conductivity type that is opposite the first conductivity type, provided within said substrate;
• a first electrode region of the second conductivity type, provided within said well region and having an impurity concentration that is higher than an impurity concentration of said well region;
• a first region of the first conductivity type, provided within said well region;
• and
• a second electrode region of the second conductivity type, provided within said substrate,
• wherein said first electrode region, said first region and said second electrode region are respectively arranged in order spaced apart from one another in a first direction,
• said first region includes a plurality of sub-regions of the first conductivity type, provided spaced apart from one another in a second direction that is orthogonal to said first direction, and
• a surface channel region is formed between adjacent sub-regions,
• wherein a first junction-type FET has a gate which is formed by said substrate and first region, a channel which is formed by said well region between said substrate and said first region, a drain which is formed by said first electrode region, and a source which is formed by said second electrode region, and
• wherein a second junction-type FET has a gate which is formed by said first region, a channel which is formed by said surface channel region, a drain which is formed by said first electrode region, and a source which is formed by said second electrode region.