Scalable split-gate flash memory cell structure and its contactless flash memory arrays

A contactless scalable split-gate flash memory array, comprising:

• a semiconductor substrate of a first conductivity type having a shallow-trench-isolation (STI) structure formed, wherein said STI structure comprises a plurality of active regions and a plurality of STI regions being formed alternately on said semiconductor substrate;
• a plurality of common-source regions and a plurality of scalable regions being alternately formed on said STI structure and transversely to the plurality of active regions, wherein each of the plurality of scalable regions comprises a pair of scalable split-gate regions being defined by a pair of third sidewall dielectric spacers formed over outer sidewalls of nearby common-source regions and a scalable common-drain region being formed between said pair of scalable split-gate regions;
• each of the plurality of common-source regions comprising a plurality of common-source diffusion regions of a second conductivity type being formed in said semiconductor substrate of the plurality of active regions, a pair of first sidewall dielectric spacers being formed over outer sidewalls of nearby scalable split-gate regions, and a first flat bed being alternately formed by said common-source diffusion region and a fifth raised field-oxide layer between said pair of first sidewall dielectric spacers, wherein a common-source conductive bus-line is formed over said first flat bed and a first planarized thick-oxide layer is formed over said common-source conductive bus-line between said pair of first sidewall dielectric spacers;
• said scalable common-drain region comprising a plurality of common-drain diffusion regions of said second conductivity type being formed in said semiconductor substrate of the plurality of active regions, a pair of fourth sidewall dielectric spacers being formed over outer sidewalls of nearby scalable split-gate regions, and a second flat bed being alternately formed by said common-drain diffusion region and a sixth raised field-oxide layer between said pair of fourth sidewall dielectric spacers, wherein a plurality of planarized common-drain conductive islands are at least formed over the plurality of common-drain diffusion regions in said second flat bed;
• each of said pair of scalable split-gate regions comprising a floating-gate region being defined by each of a pair of second sidewall dielectric spacers formed over outer sidewalls of nearby common-source regions and a select-gate region being formed between said floating-gate region and said scalable common-drain region, wherein said floating-gate region comprises a plurality of floating-gate structures being formed over tunneling-dielectric layers in the plurality of active regions and a portion of a control-gate conductive layer being at least formed over the plurality of floating-gate structures and said select-gate region comprises another portion of said control-gate conductive layer being at least formed over gate-dielectric layers in the plurality of active regions;
• each of the plurality of floating-gate structure comprising a tip-cathode line being formed between a first thermal poly-oxide layer formed over its outer sidewall and a refilled-oxide layer formed in its upper corner portion near said common-source region, wherein said tip-cathode line has a second poly-oxide layer being formed over its top portion to act as a tunneling-oxide layer;
• a capping control-gate conductive layer being formed over said control-gate conductive layer to act as a conductive word-line, wherein a planarized capping-oxide layer is formed over said capping control-gate conductive layer;
• and
• a plurality of metal bit-lines integrated with said planarized common-drain conductive islands being simultaneously patterned by a masking photoresist step, wherein said masking photoresist step comprises a plurality of masking photoresist being aligned above the plurality of active regions or a plurality of hard masking dielectric layers being aligned above the plurality of active regions and a sidewall dielectric spacer being formed over each sidewall of the plurality of hard masking dielectric layers.

A contactless scalable split-gate flash memory array, comprising:

• a semiconductor substrate of a first conductivity type having a shallow-trench-isolation (STI) structure formed, wherein said STI structure comprises a plurality of active regions and a plurality of SIT regions being alternately formed on said semiconductor substrate;
• a plurality of common-source regions and a plurality of scalable regions being alternately formed on said STI structure and transversely to the plurality of active regions, wherein each of the plurality of scalable regions comprises a pair of scalable split-gate regions and a scalable common-drain region being formed between said pair of scalable split-gate regions;
• each of the plurality of common-source regions comprising a plurality of common-source diffusion regions of a second conductivity type being formed in said semiconductor substrate of the plurality of active regions, a pair of first sidewall dielectric spacers being formed over outer sidewalls of nearby scalable split-gate regions, and a first flat bed being alternately formed by said common-source diffusion region and a fifth raised field-oxide layer between said pair of first sidewall dielectric spacers, wherein a common-source conductive bus-line is formed over said first flat bed and a first planarized thick-oxide layer is formed over said common-source conductive bus-line between said pair of first sidewall dielectric spacers;
• said scalable common-drain region comprising a plurality of common-drain diffusion regions of said second conductivity type being formed in said semiconductor substrate of the plurality of active regions, a pair of fourth sidewall dielectric spacers being formed over outer sidewalls of nearby scalable split-gate regions, and a second flat bed being alternately formed by said common-drain diffusion region and a sixth raised field-oxide layer between said pair of fourth sidewall dielectric spacers, wherein a common-drain conductive bus-line is formed over said second flat bed and a second planarized thick-oxide layer is formed over said common-drain conductive bus-line between said pair of fourth sidewall dielectric spacers;
• each of said pair of scalable split-gate regions comprising a floating-gate region being defined by each of a pair of second sidewall dielectric spacers formed over outer sidewalls of nearby common-source regions and a select-gate region being formed between said floating-gate region and said scalable common-drain region, wherein said floating-gate region comprises a plurality of floating-gate structures being formed over tunneling-dielectric layers in the plurality of active regions and a portion of a control-gate conductive island being at least formed over each of the plurality of floating-gate structures and said select-gate region comprises another portion of said control-gate conductive island being at least formed over a gate-dielectric layer in each of the plurality of active regions;
• each of the plurality of floating-gate structures comprises a tip-cathode line being formed between a first thermal poly-oxide layer formed over its outer sidewall and a refilled-oxide layer formed in its upper corner portion near said common-source region, wherein said tip-cathode line has a second poly-oxide layer being formed over its tip to act as a tunneling-oxide layer;
• a planarized control-gate conductive island being formed over said control-gate conductive island;
• and
• a plurality of metal word-lines integrated with said planarized control-gate conductive islands over said control-gate conductive islands being simultaneously patterned by a masking photoresist step, wherein said masking photoresist step comprises a plurality of masking photoresist being aligned above the plurality of active regions or a plurality of hard masking dielectric layers being aligned above the plurality of active regions and a sidewall dielectric spacer being formed over each sidewall of the plurality of hard masking dielectric layers.