Scalable vertical DRAM cell structure and its manufacturing methods

A contactless DRAM array, comprising:

• a semiconductor substrate of a first conductivity type having a plurality of active regions and a plurality of first-type shallow-trench-isolation (STI) regions formed alternately;
• a plurality of scalable trench regions and a plurality of self-aligned common-drain regions being formed alternately on said semiconductor substrate and transversely to the plurality of active regions, wherein each of the plurality of scalable trench regions comprises a plurality of paired deep-trench regions and a plurality of second-type STI regions being formed between the plurality of paired deep-trench regions in the plurality of active regions;
• the plurality of paired deep-trench regions being defined by a pair of first sidewall dielectric spacers formed over outer sidewalls of nearby self-aligned common-drain regions in each of the plurality of scalable trench regions, wherein said deep-trench region comprises:
• a trench capacitor being formed in a lower portion of a deep trench, a collar-oxide layer together with a capacitor-node connector being formed in a middle portion of said deep trench, and a vertical transistor region being formed in an upper portion of said deep trench;
• said trench capacitor comprising an upper capacitor node being formed over a capacitor-dielectric layer and said capacitor-dielectric layer being formed over a lower capacitor node in said semiconductor substrate;
• said vertical transistor region comprising a gate-dielectric layer over a portion of a sidewall of said deep trench together with a conductive-gate node being formed over an isolation silicon-dioxide node, said isolation silicon-dioxide node being formed over a source conductive node, and said source conductive node being formed over said capacitor-node connector and a portion of said collar-oxide layer to act as a dopant diffusion source for forming a common-source diffusion region in said semiconductor substrate near an outer portion of said source conductive node, wherein said conductive-gate node, said isolation silicon-dioxide node, said source conductive node, and said capacitor-node connector are patterned by a pair of second sidewall dielectric spacers being formed over outer sidewalls of said nearby self-aligned common-drain regions;
• and
• said self-aligned common-drain region comprising:
• a common-drain diffusion region of said second conductivity type being formed in said semiconductor substrate of each of the plurality of active regions, a pair of fifth sidewall dielectric spacers being formed over outer sidewalls of nearby scalable trench regions, and a flat bed being located between said pair of fifth sidewall dielectric spacers and formed alternately by said common-drain diffusion region of said second conductivity type in said active region and a first-type fourth raised field-oxide layer in said first-type STI region, wherein said active region under said common-drain diffusion region comprises a deep implant region of said first conductivity type being formed in said semiconductor substrate near a middle portion outside of said gate-dielectric layer in said vertical transistor region, said common-source diffusion region of said second conductivity type being formed in said semiconductor substrate near an outer portion of said source conductive node, and a deeper implant region of said first conductivity type being formed in said semiconductor substrate near a middle portion outside of said collar-oxide layer.