Ultra compact DRAM cell and method of making
AssigneesInternational Business Machines Corporation, Infineon Technologies AG
InventorsHeinz Hoenigschmid, Louis Lu-Chen Hsu, Jack Allan Mandelman
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Abstract
A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the trench, a buried strap which conductively connects the transfer device to the storage capacitor, wherein the transfer device has a controlled conduction channel located at a position of the arc removed from the buried strap.
Claims9
A semiconductor cell array structure comprising:
- a group of semiconductor memory cells, each said memory cell having a storage capacitor formed in a respective trench and a transfer device having a conduction path extending in a direction of a perimeter of said trench including a channel region formed in a substantially electrically isolated semiconductor region,
- a shallow trench isolation (STI) region having a substantially vertical sidewall, said STI region partially overlaying at least one of said trenches, each said substantially isolated semiconductor region extending along the outside of a substantial portion of the perimeter of said trench and adjoining said substantially vertical sidewall wherein a single STI region partially overlays a plurality of said trenches.
Dependencies are inferred from the claim text.