Integrated circuit having improved ESD protection
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Hsun Wu, Jian-Hsing Lee, Shui-Hung Chen, Jian-Ren Shih
Life of this patent
Estimating the term…
Abstract
An MOS integrated circuit, such as an input-output buffer, exhibits improved resistance to damage from electrostatic discharge (ESD) by balancing the ESD current flow through active and inactive sections of drivers. Better balance of the ESD current flow is achieved by increasing the width and length of nulti-finger channels of semiconductor material defining the gates of the drivers in the active section. Wider, longer gates of the drivers in the active section increase their ability to carry current, thereby resulting in a more symmetrical distribution of ESD current between the active and inactive sections without degrading the IC's normal performance.
Claims12
An MOS integrated circuit having improved resistance to electrostatic discharge (ESD) damage, comprising:
- a first active section of MOS devices connected between an output pad of the IC and a source of voltage;
- and,
- a second, inactive dummy section of MOS devices connected between said pad and said voltage source,
- the devices in each of said active and dummy sections being defined by a multi-finger array of channels of semiconductor material, each of said channels having a width from the source to the drain of the device, and having a length, the width of the channels forming the devices in said first active section being wider than the channels forming the devices in said second dummy section, whereby the current carrying capacity of said first active section is increased, thereby to better balance the flow of current through said first and second sections resulting from an ESD.
An MOS integrated circuit having improved resistance to electrostatic discharge (ESD) damage, comprising:
- a first active section of MOS drivers;
- a second, inactive dummy section of MOS drivers, and,
- the drivers in each of said first and second sections including a multi-finger array of channels of semiconductor material respectively defining the gates of said drivers in said sections, each of said channels having a width from the source to the drain of the device, and having a length, the width and length of the channels defining the gates of the drivers in said first section being greater than the corresponding width and length of the channels forming the drivers in said second section, whereby the current carrying capacity of said first section is increased, thereby to better balance the flow of current through said first and second sections resulting from an ESD.
Dependencies are inferred from the claim text.